Nvidia's 88-core Vera bets agentic serving runs out of bandwidth before it runs out of cores

Bandwidth per core is the number the slides leave for the reader to work out. Divide 1.2 TB/s by 88 cores and each core sits behind roughly 13.6 GB/s of memory bandwidth ^[16]. That figure, not the core count, is what a monolithic compute die and an LPDDR5X subsystem are built to protect ^[7][8].

The workloads Nvidia chose to publish reward cores. Kernel compilation and parallel headless browser instances both scale out, and Nvidia is running them against a part with eight more cores than Vera has ^[9][10][15]. Normalise the claims per core and the gap widens: 22 percent faster on a native AArch64 kernel build at 88 cores against 96 is about 33 percent more throughput per core, and the 24 percent browser-scaling win is about 35 percent ^[17][18]. Those are per-core and per-byte numbers dressed as socket numbers.

The cross-compile result is the one operators should read twice. Vera's advantage drops from 22 percent on a native AArch64 target to 14 percent when the target is x86 ^[10], which means roughly 7 percent of the win goes back to the toolchain when the fleet still builds x86 artefacts ^[19]. Agentic build chains that emit binaries for x86 hosts pay that back on every job.

Spatial multithreading is aimed at variance rather than peak. Nvidia splits core resources across two pipelines while still allowing data and cache to move between threads ^[3], and the SPEC CPU 2017 intrate demonstration measures a core alone, then with a second thread live ^[20]. Traditional SMT time-slices the resources and leaves gaps at branch prediction and decode; Nvidia's version still has threads contending, but degrades in a predictable way ^[4]. For a serving fleet, predictable degradation is worth more than a higher single-thread ceiling, because tail latency is what you have to provision against.

Which makes the missing comparator awkward. Nvidia did not say which "traditional CPU" the noisy-neighbour chart is measured against ^[20], so the single result supporting the architecture's most distinctive feature cannot be checked by anyone else. The 4.5x figure attached to the browser workflow deserves the same discipline: it comes from stripping GUI rendering, fonts and media decoding out of the browsing path ^[11], which is a property of the workload rather than of the silicon, and any CPU running the same trimmed path inherits it.

On Venice, the disclosed numbers do not exist. Tom's Hardware points to earlier coverage of how Vera stacks up against AMD's next-generation parts, but the comparisons Nvidia brought to Hot Chips 2026 are against the shipping 96-core EPYC 9655P ^[15]. So the like-for-like argument is being fought on ground Nvidia picked: one SKU ^[7], one compute die instead of compute chiplets ^[8], memory bandwidth, and consistency under load. Nvidia's own framing concedes the weakness in that ground, since it acknowledges agentic AI has no settled benchmark and that tasks such as compilation are proxies for chains that are long and inconsistent to measure ^[1][2]. A buyer comparing sockets in 2026 will be comparing a fixed 88-core part against a family, using benchmarks that stand in for the workload rather than being it.