Build1 publisher3 min readPublished
Nuvacore puts off choosing WarpCore's instruction set until much of the core is designed
Nuvacore is designing a significant part of its WarpCore data-center CPU before choosing between Arm, RISC-V and x86. The startup gets to make the instruction-set decision later, though whichever one it picks still has to shape the front end and parts of the rest of the core.
The Engineer · Build desk
Drafted by a language model from the sources cited here and checked against its claim ledger before publication. How we use AISend a correction
What happened
- Nuvacore says it will choose the instruction set later, based on what works best for the systems it and its partners plan to build.
- The company has not disclosed WarpCore's schedule, configuration, manufacturing process, power or performance targets.
- Nuvacore was founded by Gerard Williams, John Bruno and Ram Srinivasan and came out of stealth earlier this year.
- Williams and Bruno previously co-founded Nuvia, which Qualcomm acquired and whose work shaped the Snapdragon X Elite chips.
Compiled by The EngineerSomething wrong?How this is made
Why it matters
- constraint Decode and ordering logic cannot be finished until the ISA is picked, and that late work then reaches back into parts of the core already designed.
- decision Partners planning systems on WarpCore get a say in the instruction set, but until it is chosen they cannot judge software compatibility, one of the things the ISA governs.
- precedent AMD's cross-ISA plan ended for lack of resources at an established chipmaker, so any move by Nuvacore to keep more than one ISA viable would repeat the approach that failed there.
A modern high-performance core already divides roughly where Nuvacore wants to cut. Instructions are translated into internal micro-operations, so much of the execution pipeline is separated from the instruction set [4]. According to Tom's Hardware, the ISA still shapes instruction decoding, register handling, memory ordering and software compatibility [4]. The same report lists execution units, branch-prediction units, data paths, caches and portions of the memory subsystem as work that can be developed and evaluated before every ISA decision is final [8].
The company describes the order plainly. "Rather than beginning with the constraints of an existing architecture and iterating from there, we are starting with the core itself," Nuvacore said in its statement [5]. When it launched, it promised to "rewrite the rules of silicon" and did not say how [17]. This statement is the first time it has attached a method to the phrase.
The two lists meet at the memory system. Memory ordering is on the ISA-influenced list, and only portions of the memory subsystem are on the independent one [1]. Caches and data paths can be evaluated now [8]. The logic that enforces ordering rules has to wait for the instruction set [1].
The front end is the firmer limit. "Eventually, WarpCore will need front-end logic designed around its chosen instruction set, and those architectural requirements will inevitably affect other parts of the processor," Tom's Hardware wrote [7]. That supports a later decision. Nuvacore's statement does not describe carrying two instruction sets or switching after front-end work begins. The report's analysis of the front end cuts against the idea that the choice stays open once it is made [7].
AMD tried a more ambitious version. Under Rory Read and Lisa Su, it pursued an "ambidextrous" strategy meant to serve x86 and Arm customers with shared processor and platform IP [11]. SkyBridge was announced in 2014. It was to deliver pin-compatible 64-bit Arm and x86 chips, built on Puma+ and Cortex-A57 cores, with common platform infrastructure [12]. The K12 Arm core, developed under Jim Keller, was supposed to share microarchitecture features with Zen [13]. SkyBridge was scrapped for lack of resources, K12 never became a commercial product, and AMD went on with x86 Zen cores alone [14]. AMD tried to carry two instruction sets at once. Tom's Hardware sees Nuvacore taking the idea further by deliberately postponing the decision [19].
I think deferral is the right tradeoff for a small team whose target is sustained data-center throughput. Tom's Hardware ties the approach to focusing on microarchitecture and tuning for performance, power efficiency and the sustained workloads of data centers and AI infrastructure [18]. In my view, the branch predictors, execution units and caches on the independent list are where that tuning happens. The tradeoff holds until front-end design becomes the item that sets the schedule. Tom's Hardware also wonders whether Nuvacore's business plan includes selling CPUs at all [16].
What to watch
- Nuvacore's announcement of which instruction set WarpCore will use, and whether it names more than one.
- Disclosure of WarpCore's schedule, process and performance targets, which would show how late in the project the ISA choice can come.
- Whether Nuvacore sells its own chips or supplies WarpCore to partners who build the systems.