Topic

CPU Microarchitecture

The internal design of a CPU core—fetch, decode, branch prediction, execution pipelines, and cache hierarchy—that implements an instruction set.

Current stories

buildOne report1 publisher

Nuvacore puts off choosing WarpCore's instruction set until much of the core is designed

Nuvacore is designing a significant part of its WarpCore data-center CPU before choosing between Arm, RISC-V and x86. The startup gets to make the instruction-set decision later, though whichever one it picks still has to shape the front end and parts of the rest of the core.

Publishers:tomshardware.com

Reality

Evidence35
Adoption: Insufficient
Hype gap+20
Incentives: Insufficient
Confidence40

productOne report1 publisher

Arm claims 1.7x on AI models by doubling the matrix units inside its CPU cluster

The uplift runs through the regular instruction pipeline, so adopting it costs a developer a compile step. That changes what an accelerator-specific inference path has to prove before a team keeps paying to maintain it.

Publishers:androidauthority.com

Reality

Evidence38
Adoption15
Hype gap+34
Incentives70
Confidence44

productOne report1 publisher

Apple's M6 is a 2nm inference upgrade with a CPU refresh attached

The published deltas put the Neural Engine at 2x and multithreaded CPU at 1.2x. Apple's own workload figures widen that gap further, and the lineup stops at base tier.

Publishers:macrumors.com

Reality

Evidence44
Adoption22
Hype gap+28
Incentives68
Confidence41

buildOne report1 publisher

Nvidia's 88-core Vera bets agentic serving runs out of bandwidth before it runs out of cores

One SKU, one compute die, 1.2 TB/s of LPDDR5X, and benchmark wins over a 96-core EPYC. The comparison with AMD's Venice is being set on Nvidia's terms rather than on core counts.

Publishers:tomshardware.com

Reality

Evidence38
Adoption12
Hype gap+33
Incentives78
Confidence44

buildOne report1 publisher

IBM put an Arm decoder in a mainframe core, and only half the consolidation pitch has a native path

The dual-ISA core runs AArch64 and z/Architecture on the same core with nanosecond switching. x86 is named in the pitch and absent from the silicon, and the uptime arithmetic does not close.

Publishers:tomshardware.com

Reality

Evidence44
Adoption8
Hype gap+34
Incentives72
Confidence47