SK hynix locates the next AI inference bottleneck in the data moving between HBM, DRAM and SSDs
SK hynix's Ahn Hyun projects AI infrastructure performance needs will grow roughly 19 to 20 times by 2030, citing inference demand. The company's answer is to tune the whole memory hierarchy, from HBM down to SSDs, and to add 3D stacked DRAM and a NAND-based HBF.
The Investor · Invest desk
Three figures. HBF capacity target: roughly 10 times comparable-generation HBM, per the Korea Herald. Capacity per unit of bandwidth: about 20 times HBM, from 10 times capacity at about half the bandwidth. Growth in AI infrastructure performance scale by 2030, per Yonhap: roughly 20-fold.
| Figure | Value | Note | Claim |
|---|---|---|---|
| HBF capacity target vs comparable-generation HBM, roughly | 10 times | 8 | |
| HBF capacity per unit of bandwidth vs HBM, about | 20 times | 10 times capacity at about half bandwidth | 16 |
| AI scale by 2030, Yonhap | 20 times, roughly | 3 |
What happened
- Ahn said the constraint is shifting from the gap between processors and memory to the cost of moving data across layers running from HBM and conventional DRAM down to solid-state drives.
- Yonhap reported that growing key-value cache capacity requirements, which store and reuse information a model has already processed, are forcing data to be spread across HBM, DRAM and SSDs.
- For HBF, the Korea Herald reported, SK hynix is aiming for roughly 10 times the capacity of comparable-generation HBM at about half its bandwidth.
- The company's 3D stacked DRAM would sit directly above processors such as graphics and neural processing units, shortening the distance data travels to raise speed and cut power use.
Why it matters
- decision Buyers of inference hardware have to decide how a key-value cache is split across HBM, DRAM and SSDs, and SK hynix is arguing that movement between those tiers is where the bottleneck now sits.
- capability At 10 times the capacity for half the bandwidth, HBF would offer 20 times as much capacity per unit of bandwidth as HBM, a tier aimed at data that is read often and written comparatively little.
- contradiction The Korea Herald reports 19-fold and Yonhap 20-fold, a gap of about 5% in the multiple that shrinks to about 1.3% in the implied yearly rate, so the direction of the argument holds on either figure.
Compounded over the four years from 2026, a 19-fold requirement works out to about 2.1 times a year, and so does a 20-fold one [14]. On either figure the performance that AI infrastructure has to deliver slightly more than doubles every year until 2030. The multiple describes performance, so memory demand has to be inferred from it. Ahn's own account of the drivers, as Yonhap relayed it, has three parts: task complexity, the amount of information processed at a time, and the volume of inference requests [6].
Both outlets are reporting the same keynote, delivered by an executive of a memory maker presenting its roadmap [1], so the multiple is SK hynix's own projection. We think the roadmap does point to memory spending beyond HBM. SK hynix says it will optimize the entire memory hierarchy and not only individual chips, while HBM development, including versions customized to customers' AI architectures, continues [10]. It also plans to advance Compute Express Link and next-generation storage [11].
Neither report includes a capex figure, a ship date or a customer for HBF or 3D stacked DRAM. The only customer-side item in the Korea Herald's account is an Nvidia Vera Rubin superchip on show at SEDEX beside an HBM wafer signed by Nvidia CEO Jensen Huang [13].
HBF is the piece most exposed to that gap. Ahn stressed the importance of industry standards for HBF and of cooperation with global technology partners [11], and without both it is one company's format. SK hynix sees particular potential for it in workloads that repeatedly read large volumes of data and write comparatively little [12]. We would be wrong if buyers meet key-value cache growth by adding HBM and DRAM and leave the SSD tier alone [5], or if processors absorb most of the 19-to-20-fold requirement and memory's share turns out small.
What to watch
- Whether HBF gets an industry standard and named partners, which Ahn said the technology needs.
- Any capex figure, ship date or customer for HBF or 3D stacked DRAM from SK hynix.
- Whether SK hynix states which multiple, 19 or 20, it presented, and how much of it falls on memory rather than processors.
Clarity's read
What the record supports and how the coverage leans. The claims behind it follow.
Reality
- Evidence35
- Adoption
- Insufficient
- Hype gap
- Insufficient
- Incentives70
- Confidence65
Claim ledger
Ranked by verification strength, evidence, and original report placement.
- [1]
Ahn Hyun, president and chief development officer of SK hynix, outlined the company's next-generation memory road map in a keynote speech at SEDEX 2026, a semiconductor exhibition in Seoul, on Wednesday (Oct. 14).
- [2]
Ahn projected that AI infrastructure performance requirements could grow roughly 19-fold by 2030 compared with 2026.
- [3]
SK hynix projected that the performance scale of AI infrastructure will grow roughly 20-fold by 2030, driven by rapidly rising demand for AI inference.
- [4]
Ahn said the challenge is shifting from the traditional gap between processors and memory to bottlenecks caused by moving data across different memory layers, from HBM and conventional DRAM to solid-state drives.
- [5]
Growing capacity requirements of key-value (KV) caches, which store and reuse information previously processed by AI models, are requiring data to be distributed across different types of memory, including HBM, DRAM and SSDs.
- [6]
Ahn said the AI inference market is expanding simultaneously in three areas: task complexity, the amount of information processed at a time, and the volume of inference requests.
- [7]
SK hynix's 3D stacked DRAM places memory directly above processors such as graphics and neural processing units, shortening the distance data must travel to improve processing speeds and reduce power consumption.
- [8]
SK hynix aims for HBF to deliver roughly 10 times the capacity of comparable-generation HBM at about half its bandwidth.
- [9]
HBF applies advanced stacking and high-speed data transfer technologies developed for HBM to NAND flash memory.
- [10]
SK hynix plans to optimize the entire memory hierarchy rather than focus solely on improving individual chips, while continuing HBM development, including customized versions tailored to customers' AI architectures.
- [11]
SK hynix also plans to advance Compute Express Link and next-generation storage technologies, and Ahn emphasized the importance of establishing industry standards for HBF and strengthening cooperation with global technology partners.
- [12]
SK hynix sees particular potential for HBF in workloads that repeatedly read large volumes of data while requiring relatively fewer write operations.
- [13]
The SEDEX exhibition featured an Nvidia Vera Rubin superchip and an HBM wafer signed by Nvidia CEO Jensen Huang.
- [14]
Compounded over the four years from 2026 to 2030, a 19-fold increase is about 2.09 times a year and a 20-fold increase about 2.11 times a year, so about 2.1 times a year on either figure.
- [15]
The Korea Herald's 19-fold and Yonhap's 20-fold differ by about 5% in the multiple, which shrinks to about 1.3% in the implied yearly growth rate.
- [16]
HBF's target of 10 times the capacity at about half the bandwidth of comparable-generation HBM is about 20 times the capacity per unit of bandwidth.
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Sources
2 independent publishers whose own reporting we read for this story.
- en.yna.co.krSK hynix projects AI infrastructure performance to grow 20-fold by 2030
1 article · October 13, 2026
- koreaherald.comSK hynix looks beyond HBM to tackle AI memory bottlenecks
1 article · October 13, 2026
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