Counterpoint's 12-layer Rubin forecast keeps more DRAM wafers tied up in HBM

SK hynix's own parts give the scale. Its 12-layer HBM4 holds 36GB and its 16-layer version holds 48GB ^[5]. Both work out to 3GB a die ^[16]. That means a stack's capacity rises with its die count, and so does the DRAM silicon it uses. At that density an eight-layer stack would hold 24GB, or 12GB less than a 12-layer one ^[17].

Suppose the Korea Herald's figure that HBM takes more than three times the wafer capacity of conventional DRAM applies per gigabyte. Then those 12GB tie up capacity that could have made more than 36GB of conventional DRAM, stack by stack ^[19]. Counterpoint backed the eight-layer design in its August report ^[3], so the same firm has now argued for both layer counts since the summer. The report does not include DRAM prices. The Korea Herald presents the pricing effect as a possibility: sustained AI demand could keep standard memory supplies tight even as chipmakers expand production ^[14].

The forecast leaves three possible outcomes. Counterpoint could be right, and 12-high stacks would hold wafers in HBM through the Rubin cycle ^[1]. It said "most", so some Rubin products may still use eight layers ^[1]. The third outcome is that packaging sets the ceiling. HBM has to be joined to the GPU on TSMC's chip-on-wafer-on-substrate lines, and limited packaging capacity could hold back finished accelerators even when there is enough memory ^[11]. I'd expect packaging to limit volumes first. Against that, a packaging shortage slows how fast Rubin ships without changing how many dies each stack needs, so the wafers each accelerator uses stay where Counterpoint's forecast puts them. If conventional DRAM supply loosens while Rubin ships on 12-high stacks, the wafer argument is wrong.

SK hynix has been mass supplying HBM4 to major customers since the second quarter and has expanded production since then ^[6]. It has also been working with TSMC to fit its HBM to TSMC's packaging ^[12]. Samsung has shipped 12-layer HBM4 of up to 36GB since February ^[8]. Its development work is going into hybrid copper bonding for stacks of 16 or more dies, a technique meant to lower thermal resistance as die counts rise ^[10].

An industry source who spoke to the Korea Herald on condition of anonymity said: "Being first to develop 16-layer technology matters less than achieving the yields and packaging compatibility customers actually need. The pace of supply expansion will ultimately depend on how well memory makers' capabilities align with TSMC's packaging capacity." ^[13]