The maintenance ledger is where this lands first. A team shipping on-device inference keeps a device matrix, and every row on it is a promise that a given chip gets a given code path. Arm's claim about SME2 goes straight at that ledger: the instructions execute as part of the regular CPU instruction pipeline, so the work required of a developer is compiling them in and nothing else [13].
Arm's own description carries the caveat a sentence later. Putting a second SME2 unit in the shared cluster does not double throughput; the two units run in parallel, so the extra one pays off only where the AI workload can be split [11][14]. The rest of the advertised gain is credited to faster low-precision math and to Lookup Table Instructions that cut memory bandwidth demand [10].
Put the two headline numbers side by side and the design budget shows. Peak general performance is up to 15% over the C1-Ultra, of which 8 points are the clock moving to 4.45GHz, leaving 7 points to the architecture [3][4]. The AI number is up to 1.7x, which is 70% [10]. Seventy divided by fifteen is about 4.7, so the AI-specific claim is roughly four and a half times the general one [1]. Efficiency runs the same direction: equal performance at 38% less power is 1 divided by 0.62, close to 1.6x the work per watt [5][2], on a core whose pipeline is no wider than last year's and whose general gains come from holding about 2600 instructions in flight instead of 2000 [7].
None of these figures is a usage measurement. The power number is a battery claim, the 1.7x is a throughput claim, and both are Arm's.
Gating is where a rollout goes wrong. Xiaomi's XRING O3 already runs two SME2 units on last year's C1 architecture [12], so a fast path switched on by core generation is wrong about at least one chip already in the market, and wrong in the direction that leaves silicon idle. A device matrix inherits assumptions faster than it retires them.
What matters per accelerator path is two numbers: the throughput multiple that path buys over the compiled CPU path on the model in question, and the count of shipping devices where that multiple has actually been measured. Every figure Arm has published here compares this year's core to last year's; none of them compares a CPU path to a dedicated NPU [4], so the multiple has to come off an in-house bench. Where a measured advantage exists, the accelerator path earns its keep. Where it does not, the compiled path becomes the default by omission, and the tradeoff is throughput left unused on chips whose accelerator was never benchmarked.
The 2027 flagship story does not extend down the price list either. The C2-Premium, C2-Pro and C2-Nano are described as last year's cores retuned for area, efficiency and power on 2nm [9], so a CPU-first inference plan needs its fallback tested on the cheap phones most of the install base actually buys.
