Build1 distinct publisher3 min readUpdated
Contract prices roughly tripled in two quarters. Marvell is selling recycled DDR4 behind CXL, but its reference customer, Meta, did the job on an ASIC of its own design.
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Meta's case for salvage does not start with price. Its paper puts server life at three to five years and the DRAM inside at seven to 10 [16], so the modules outlive the chassis they shipped in by two to seven years [6]. Around 40% of the fleet is memory-capacity bound [16]. The shortage and the surplus are in the same building.
The part that closes the gap is deliberately unambitious: a CXL 2.0 Type-3 expander on a PCIe 5.0 x16 link, bridging two DDR4 channels, 128GB per chip assembled from 32GB modules pulled out of retired machines [14]. That works out to four salvaged modules per chip and two chips per MemServer to reach the 256GB of DDR4-2400 sitting beside 768GB of local DDR5-6400 [5]. A quarter of each machine's memory is second-hand [4], at a claimed 50ns idle round trip on the controller path [15], and server counts for disaggregated ML inference fall by up to 25% [13].
Supply is the part that caps the idea. Samsung, SK hynix and Micron have been winding DDR4 down since last year, and TrendForce measured the legacy rally at up to 50% for DDR4 in Q1 alone [6]. No new DDR4 is coming, so the pool of poolable memory is whatever you bought in 2021 and 2022 and are retiring now. This scales with your own decommissioning calendar, not with anyone's fab.
The ladder underneath is steep. Contract prices rose 90 to 95% in Q1 2026 and another 58 to 63% in Q2 [2][3], which compounds to roughly 3.0 to 3.2 times in two quarters [1], and 3.4 to 3.8 times by the end of Q3 if server DRAM lands inside the forecast 13 to 18% [4][2]. U.S. hyperscalers capped part of that with long-term agreements running through 2027 and 2028 [4]. Buyers without one were already being filled at about 70% of orders late last year, while wafers went to HBM [5].
Marvell answers this on a slower clock. The Structera X expansion controllers were announced in July 2024 and are in hyperscaler deployments, with inline LZ4 that VP Khurram Malik told EE Times returns 2 to 2.5 times effective capacity [9]; on Meta's 256GB that would read as 512 to 640GB [8]. The Structera S switch samples this quarter [10], and the one genuinely new part, the Bravera SC6, samples in Q4 and puts drives in 2027 at the earliest [8]. The switch's under-460ns round trip is roughly nine times Vistara's idle figure [7], for a different job: 48TB shared across 16 or 32 sockets at 4 TB/s [10] rather than two channels bolted to one host.
So the three-tier portfolio is an assembly. The optical tier came in with the $3.25 billion Celestial AI purchase that closed in February [11], and in March Marvell took $2 billion from Nvidia tied to NVLink Fusion, the proprietary scale-up fabric that CXL pooling has to sit alongside [12]. In 2024, DDR4 reuse was a sustainability line; the crunch turned it into a capex line [17]. The proof point for that argument is a socket Marvell does not hold [13].
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Ranked by verification strength, evidence, and original report placement.
Structera X 2404 and X 2504, the DDR4 and DDR5 expansion controllers, were announced in July 2024 and are both in hyperscaler deployments, with inline LZ4 compression that Malik told EE Times yields roughly 2 to 2.5 times the effective capacity.
Marvell took a $2 billion investment from Nvidia in March, tied to NVLink Fusion, the proprietary scale-up fabric CXL pooling has to sit alongside.
Meta is already running recycled DDR4 behind CXL across millions of servers, cutting server counts by up to 25% for some inference workloads, and did it with an ASIC of its own design rather than anything from Marvell.
Memory will account for roughly 30% of hyperscaler capex this year, up from about 8% in 2023 and 2024.
Conventional DRAM contract prices rose 90% to 95% quarter-on-quarter in Q1 2026, the steepest increase on record for every DRAM category.
Evidence-backed comparisons of source perspectives and observed adoption signals. Read the methodology
Which Builder, Operator, and Investor concerns the observed source mix emphasized—not a truth score.
Evidence, demonstrated adoption, hype gap, incentives, and confidence are assessed independently, each on its own current evidence. How these are measured.
Detailed but single-publisher, largely vendor- and paper-sourced
The reporting is specific and traceable to named primary material — Marvell's product and FMS blogs, an EE Times interview with a named VP, Meta's ISCA 2026 paper (read via The Register), TrendForce pricing, Yole penetration estimates and a SemiAnalysis architectural argument. But it is one outlet's account, no vendor claim is independently tested, and the Structera X customer is unnamed.
Real at one hyperscaler on custom silicon; merchant CXL still near zero
Recycled-DDR4-behind-CXL is genuinely in production at millions-of-server scale, but on Meta's own ASIC, chassis and page-placement stack. Merchant adoption is thin: Structera X deployments are asserted without a named customer, Structera S is only now sampling, Bravera SC6 samples in Q4 2026 with drives in 2027, and Yole puts servers actually using CXL near zero today rising to just 13% by 2030. Astera Labs' Azure M-series preview is the one named third-party design win.
Portfolio framing outruns shipping content and CXL uptake
The market pressure is real and well quantified, but the vendor narrative is overstated relative to what is shipping: a 'three-tier AI memory infrastructure' launch in which only one part is new and does not sample until Q4 2026, an acquired optical tier carrying a 2-3x token throughput claim, and a headline CXL use case whose flagship practitioner built its own ASIC instead. Yole's near-zero present-day CXL usage further widens the gap. The article itself flags this, which keeps the gap moderate rather than severe.
Vendor-launch reporting with a strategic-investor overlay
The core material is a supplier's conference launch, promoted through a product marketing VP's interview and Marvell's own blogs and benchmarks, in a market where memory scarcity makes reuse pitches commercially valuable. Marvell also carries a $2B Nvidia investment tied to NVLink Fusion, shaping where its CXL story is aimed. Countervailing incentives exist — Meta's academic disclosure and third-party TrendForce, Yole and SemiAnalysis figures — but the agenda is vendor-set.
Specific and checkable, but unreplicated and partly forward-looking
Figures are precise and attributed to identifiable primary sources, and the derived multiples follow arithmetically from the reported ranges. Confidence is held down by the single-publisher cluster, reliance on vendor assertions for merchant adoption, a Q3 pricing figure that is still a forecast, one source passage truncated mid-attribution, and Meta's results reaching the reader second-hand.
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