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Memory is 30% of hyperscaler capex, and the cheapest fix is the DDR4 you already own
Contract prices roughly tripled in two quarters. Marvell is selling recycled DDR4 behind CXL, but its reference customer, Meta, did the job on an ASIC of its own design.
The Engineer · Build desk
What happened
- Memory is on track for roughly 30% of hyperscaler capex this year, against about 8% in 2023 and 2024.
- Conventional DRAM contract prices rose 90% to 95% quarter-on-quarter in Q1 2026, the steepest move on record for every DRAM category.
- Meta runs recycled DDR4 behind CXL across millions of servers, cutting server counts by up to 25% on some inference work, using an ASIC of its own design.
- Marvell brought a three-tier AI memory portfolio to FMS 2026 on August 4, with DDR4 reuse at the top of its CXL use-case list.
Why it matters
- constraint With all three big makers retiring DDR4 lines, no operator can order more of the cheap tier; the ceiling is set by its own decommissioning calendar.
- cost The largest buyers pre-hedged part of the climb to 2027 and 2028, so the compounded ladder is absorbed by everyone buying server DRAM without such a contract.
- decision Anyone weighing disaggregation this year is choosing between waiting on merchant silicon that lands in 2027 and funding an in-house expander now.
- exposure Merchant controller vendors are left selling to the operators that cannot pay for their own silicon, which is where their pricing power now sits.
Meta's case for salvage does not start with price. Its paper puts server life at three to five years and the DRAM inside at seven to 10 [16], so the modules outlive the chassis they shipped in by two to seven years [25]. Around 40% of the fleet is memory-capacity bound [16]. The shortage and the surplus are in the same building.
The part that closes the gap is deliberately unambitious: a CXL 2.0 Type-3 expander on a PCIe 5.0 x16 link, bridging two DDR4 channels, 128GB per chip assembled from 32GB modules pulled out of retired machines [14]. That works out to four salvaged modules per chip and two chips per MemServer to reach the 256GB of DDR4-2400 sitting beside 768GB of local DDR5-6400 [24]. A quarter of each machine's memory is second-hand [23], at a claimed 50ns idle round trip on the controller path [15], and server counts for disaggregated ML inference fall by up to 25% [3].
Supply is the part that caps the idea. Samsung, SK hynix and Micron have been winding DDR4 down since last year, and TrendForce measured the legacy rally at up to 50% for DDR4 in Q1 alone [9]. No new DDR4 is coming, so the pool of poolable memory is whatever you bought in 2021 and 2022 and are retiring now. This scales with your own decommissioning calendar, not with anyone's fab.
The ladder underneath is steep. Contract prices rose 90 to 95% in Q1 2026 and another 58 to 63% in Q2 [5][6], which compounds to roughly 3.0 to 3.2 times in two quarters [20], and 3.4 to 3.8 times by the end of Q3 if server DRAM lands inside the forecast 13 to 18% [7][21]. U.S. hyperscalers capped part of that with long-term agreements running through 2027 and 2028 [7]. Buyers without one were already being filled at about 70% of orders late last year, while wafers went to HBM [8].
Marvell answers this on a slower clock. The Structera X expansion controllers were announced in July 2024 and are in hyperscaler deployments, with inline LZ4 that VP Khurram Malik told EE Times returns 2 to 2.5 times effective capacity [1]; on Meta's 256GB that would read as 512 to 640GB [19]. The Structera S switch samples this quarter [12], and the one genuinely new part, the Bravera SC6, samples in Q4 and puts drives in 2027 at the earliest [11]. The switch's under-460ns round trip is roughly nine times Vistara's idle figure [26], for a different job: 48TB shared across 16 or 32 sockets at 4 TB/s [12] rather than two channels bolted to one host.
So the three-tier portfolio is an assembly. The optical tier came in with the $3.25 billion Celestial AI purchase that closed in February [13], and in March Marvell took $2 billion from Nvidia tied to NVLink Fusion, the proprietary scale-up fabric that CXL pooling has to sit alongside [2]. In 2024, DDR4 reuse was a sustainability line; the crunch turned it into a capex line [17]. The proof point for that argument is a socket Marvell does not hold [3].
What to watch
- Whether Q3 server DRAM lands inside the forecast 13% to 18%, and what happens to buyers when the hyperscaler long-term agreements run out in 2027 and 2028.
- Whether Bravera SC6 holds its Q4 sampling date, and whether Phison or Silicon Motion get Gen6 drives out ahead of it.
- Whether any operator other than Meta puts recycled DDR4 behind a merchant CXL controller rather than an expander it designed itself.
Clarity's read
What the record supports and how the coverage leans. The claims behind it follow.
Reality
- Evidence63
- Adoption38
- Hype gap+33
- Incentives74
- Confidence58
Claim ledger
Ranked by verification strength, evidence, and original report placement.
- [1]
Structera X 2404 and X 2504, the DDR4 and DDR5 expansion controllers, were announced in July 2024 and are both in hyperscaler deployments, with inline LZ4 compression that Malik told EE Times yields roughly 2 to 2.5 times the effective capacity.
- [2]
Marvell took a $2 billion investment from Nvidia in March, tied to NVLink Fusion, the proprietary scale-up fabric CXL pooling has to sit alongside.
- [3]
Meta is already running recycled DDR4 behind CXL across millions of servers, cutting server counts by up to 25% for some inference workloads, and did it with an ASIC of its own design rather than anything from Marvell.
- [4]
Memory will account for roughly 30% of hyperscaler capex this year, up from about 8% in 2023 and 2024.
- [5]
Conventional DRAM contract prices rose 90% to 95% quarter-on-quarter in Q1 2026, the steepest increase on record for every DRAM category.
- [7]
Server DRAM is set to climb a further 13% to 18% in Q3, held in check mainly by the long-term agreements U.S. hyperscalers signed to cap pricing through 2027 and 2028.
- [8]
Server DRAM buyers in the U.S. and China were receiving about 70% of their orders late last year as suppliers diverted wafers to HBM.
- [9]
Samsung, SK hynix and Micron have all been winding down DDR4 output since last year, and TrendForce put the legacy memory rally at up to 50% for DDR4 in Q1 alone.
- [10]
Marvell announced a three-tier "AI memory infrastructure" portfolio at FMS 2026 in Santa Clara on August 4, pitched to EE Times, where product marketing VP Khurram Malik put DDR4 reuse at the top of the CXL use-case list.
- [11]
Only one piece of the portfolio is new, the Bravera SC6 PCIe 6.0 SSD controller, which samples in Q4 2026; that puts drives in 2027 at the earliest on the timeline Tom's Hardware Premium laid out, with Phison and Silicon Motion chasing the same Gen6 launches.
- [12]
The Structera S 30260 switch, announced at OFC in March, carries 260 PCIe 6.0 and CXL 3.x lanes, connects 16 or 32 CPUs or GPUs to up to 48TB of shared memory at 4 TB/s aggregate bandwidth and under 460ns round trip, and begins sampling this quarter.
- [13]
Photonic Fabric arrived with the $3.25 billion Celestial AI acquisition that closed in February; Marvell now describes it as a shared-memory tier reaching up to 50 meters with up to 32TB of warm KV cache and a claimed 2 to 3 times token throughput inside existing footprints.
- [14]
Meta's Vistara ASIC, presented at ISCA 2026 in late June, is a CXL 2.0 Type-3 expander on a PCIe 5.0 x16 link that bridges two DDR4 channels to a host and runs at 128GB per chip using 32GB modules recovered from retired machines.
- [15]
Each MemServer pairs a 158-core AMD EPYC Turin with 768GB of local DDR5-6400 and 256GB of CXL-attached DDR4-2400, and Meta claims idle round-trip latency of around 50ns on the controller path.
- [16]
Meta's paper states that around 40% of its fleet is memory-capacity bound, and that its servers last three to five years while the DRAM inside them is good for seven to 10 years.
- [17]
When Marvell first pitched DDR4 reuse in 2024 it was a sustainability line item; two years later the memory crunch has turned it into a capex line item.
- [18]
A module pulled from a decommissioned 2021 server is now worth a multiple of what it was when Structera X was announced, and the DDR5 that would replace it has roughly doubled in price twice.
- [19]
Marvell's claimed LZ4 multiplier applied to a MemServer's 256GB of recycled DDR4 would present as 512GB to 640GB of effective capacity.
- [20]
Compounding the two reported quarters, DRAM contract prices stand at roughly 3.0 to 3.2 times their pre-Q1 level.
- [21]
If server DRAM lands inside the Q3 forecast, the two-and-a-half quarter move is roughly 3.4 to 3.8 times.
- [22]
Memory's share of hyperscaler capex has multiplied by about 3.75 times against the 2023-2024 baseline.
- [23]
Recycled DDR4 is 25% of a MemServer's installed memory capacity.
- [24]
Each Vistara chip holds four salvaged 32GB modules, and each MemServer carries two such chips.
- [25]
The rated life of the DRAM exceeds the life of the server it ships in by two to seven years.
- [26]
The Structera S switch's stated round-trip ceiling is about nine times Meta's idle figure for the Vistara controller path, across different topologies.
Sources
1 independent publisher whose own reporting we read for this story.
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