Oxidising 0.3 nanometres of aluminium gives MoS2 a gate stack equivalent to 1nm of silicon dioxide

The step someone else has to reproduce is the oxidation. Aluminium goes down as a metal film and comes back as an oxide about 1.4 times as thick, a gain of 0.12 nanometres ^[17]. That gain has to come out the same everywhere on a wafer. The researchers describe their own version as a carefully controlled oxidation following an ultrahigh-vacuum deposition ^[9].

The buffer exists because molybdenum disulfide is an awkward surface to build on. Its surface lacks the dangling chemical bonds that conventional insulators need, so those insulators struggle to form a smooth, continuous layer on it ^[4]. The defects left behind cause two problems: current leaks through them, and they scatter electrons moving in the channel underneath, which cuts carrier mobility ^[5]. "Making the insulator thinner was only part of the challenge," said Professor Wen-Hao Chang of NYCU, the study's corresponding author ^[10]. "We also needed to safeguard the atomically thin semiconductor beneath," he said ^[11]. The aluminium oxide gives the main dielectric something uniform to form on, and it also keeps electrical disturbance from that dielectric away from the channel ^[6].

Gate control gets stronger the closer the gate sits to the channel, so the insulator keeps being pushed toward a few atoms thick ^[15]. The authors say their result addresses a three-way trade-off in 2D electronics: an extremely thin gate dielectric, strong electrostatic control and high electron mobility in the same device ^[8]. Interesting Engineering's write-up left out which main dielectric was used and how many devices were measured ^[18].

This one is for the gate-stack engineers. Anyone choosing a channel material for a product this year can skip it. When the next 2D-transistor result comes through, two things are worth checking: which of the three legs were measured on one device, and which steps of the flow a fab could run tomorrow. The NYCU group has the first ^[7]. By its own account, all three of its process steps still need simplifying and scaling before a fab could run them ^[9].

"When transistor components are just a few atomic layers thick, the interface becomes an integral part of the device, not just a boundary," said Professor Tsung-En Lee of TSMC and NYCU ^[12].