Huawei claims stacked circuits deliver the density lithography would need three years to reach

Take the density claim first, because it is the one place in this announcement where an outsider can check the arithmetic: 238 million transistors per square millimetre against 155 million is 83 million more, and 83 over 155 is 53.5%, so TrendForce's figure, which it drew from Huawei's own updated paper, reconciles ^[8][1]. That density figure describes the transistor count alone; the 42% gain Huawei reports is a comparison against last year's tri-fold ^[3], and nothing in the material says the Kirin 9050 Pro is a LogicFolding part; LogicFolding is described as the circuit-level implementation of the Tau Scaling Law that Huawei presented on 25 May at IEEE ISCAS in Shanghai, built on stacked active layers and shorter connecting wires ^[6][7], and the accelerator meant to carry it, the Ascend 990, is dated 2030 ^[15].

The commercial base underneath all of this is thin. A $2,979 tri-fold ^[2], Counterpoint's forecast of 24% of foldables for Huawei by 2026, and foldables at 1.6% of handset share last year ^[5] multiply out to roughly four tenths of one percent of smartphone units ^[2]. As a P&L line that is a rounding error, which is why the launch reads as a showcase.

Then there is the number that actually prices something. Bernstein expects Nvidia's China AI-chip share to fall from about 40% in 2025 to about 8% in 2026, with Huawei above 50% ^[17], and 40 to 8 is 32 points, four fifths of the position ^[4], arriving four years before the Ascend 990 ships ^[8]. That shift is not an architecture story. The survey putting Chinese executives' local-brand allocation at 46% of accelerator budget next year against 30% now is a purchasing decision, a 16-point move ^[16][5], and CSIS's reading that export controls accelerated localisation ^[18] describes procurement behaviour rather than physics. Nvidia's H200 return to China lands into exactly that, according to Cryptopolitan ^[19].

Stacking layers and shortening wires raise transistors per square millimetre, a different metric from square millimetres per month. Huawei is reportedly still funding domestic makers of advanced DUV and other tools, which the source frames as evidence that architecture fills part of the gap rather than replacing manufacturing progress ^[14], and China's proven capability is still put at about 7nm ^[13]. The 2031 target is density equivalent to a 1.4nm process, not fabrication on one ^[12], while TSMC's 1.4nm mass production is planned for 2028, three years earlier ^[13][3].

The more useful read here: ASML and TSMC holders are being shown a claim about 2030 and 2031, while Nvidia holders are being shown next year's order book, and only one of those has a third-party forecast attached to it. The counter-case is not weak. Huawei says 381 chips have been developed and mass-produced on Tau principles across more than six years, about 63 a year ^[10][6], which is a production record rather than a conference slide, and He Tingbo's line that "in the coming 10 years our solutions for mobile computing and AI computing will be competitive" ^[11] is what a company says when the capacity conversation is already settled internally. The pool is large enough for either version to matter, with the Semiconductor Industry Association putting AI data-centre infrastructure spend before 2028 at $4 trillion or more and semiconductors at as much as $2.8 trillion, or about 70% of it ^[20][7]. This read is wrong if Nvidia's China share is still near 40% at the end of 2026, or if a LogicFolding Ascend part ships well ahead of the 990's date.