In a tunnel, a driver asks the car to reroute around the queue at a charger. That request is either answered by what is already in the car or it waits for signal to come back. Everything a spec-sheet argument about TOPS is trying to settle shows up to the driver in that one gap.
Xiaomi has not published a TOPS figure for the D100, and the 700-to-1,000 numbers circulating are unconfirmed [4]. What it did publish is 160GB of unified memory alongside a 20-core CPU and a 16-core NPU [2], plus support for locally deployed models of up to 200 billion parameters [3]. Weights have to sit somewhere, so the memory line is what makes the parameter line legible, and it is the line a procurement spec can actually be written against.
For scale on the throughput question, XPeng runs four of its in-house Turing chips in its GX robotaxi platform for a claimed 3,000 TOPS [8], which works out at 750 TOPS per chip [12]. That sits inside the unconfirmed band being guessed for the D100 [14]. On the numbers available, then, Xiaomi's real purchase looks less like raw throughput nobody else has and more like somewhere for a large model to live.
The entry fee is disclosed, which is unusual and useful. Xiaomi says it has put more than 21 billion yuan, roughly $3.1bn, into its semiconductor program and now runs a chip team of nearly 3,000 people [9]. That is about $1m of cumulative program spend per person on the team [13], before a single customer car ships with the part. Xiaomi says the D100 has reportedly completed validation but has not identified the first production vehicle [10].
Separate the thing being pitched from the thing being done. The pitch is independence from a supplier. The work is cost control at volume: Xiaomi's stated reason for owning the chip, the domain controller and the software stack is component cost as production volumes rise [6]. Its existing SU7 and YU7 rely on Nvidia automotive computing platforms [5], so this is a replacement program with a year attached, swapping into a design already in production.
For a team picking a compute target for a 2027 program, two things decide it and neither is peak throughput. First, whether you control the model that runs on the part. Second, whether your volume amortises a chip team at the scale Xiaomi has disclosed [9]. Both yes and you build, accepting that your silicon schedule now gates your feature schedule. Model yes, volume no, and you stay a buyer, spending your leverage on memory capacity and portability rather than TOPS, because the parameter budget is what your features are made of. Volume yes, model no, and your real supplier conversation is the domain controller and the bill of materials. Neither, and the honest plan assumes your chip target changes once mid-program and budgets the port.
The broader read from the source is that custom silicon stays expensive enough to remain an option mainly for automakers with large volumes and deep pockets [11]. Below that line, the negotiation worth having with a merchant vendor is about memory ceilings and how easily your model moves, not headline operations per second.
