The split that decides all of this is wafer-to-wafer versus die-to-wafer. Wafer-to-wafer joins two full patterned wafers face to face and dices them afterwards, so alignment happens once at wafer scale [12]. That is where the tight numbers come from: imec and EV Group showed a 200-nanometre pitch with post-bond overlay under 40 nanometres at ECTC in May [14]. The price is that both wafers must carry identically sized dies, and every die gets bonded whether it tested good or not, so a single bad die ruins its partner [13].
An HBM stack cannot pay that. Memory needs pre-tested dies and the freedom to mix die sizes and process nodes, which means die-to-wafer [15]. The best die-to-wafer pitch at ECTC 2026 was CEA-Leti's 1 micron, roughly five times looser than the wafer-to-wafer record [17]. And because dies go down one at a time [16], the bonder sets the ceiling: Applied Materials and Besi cite around 1,600 placements per hour on the Kinex platform, and Besi's Chameo is rated near 2,000 chips per hour [18]. At 1,600 per hour, that is one placement every 2.25 seconds [23]. Multiply by the die count in a high stack and hybrid-bonded memory becomes a capacity question before it is a pitch question.
The height budget is why the rule change bites. Microbumps have only tightened toward 10 microns for the latest memory [10], while hybrid bonding starts at 6 and has 4.5- and 3-micron generations in development [11]. A taller stack allowance is exactly what lets a pitch that loose survive another product generation.
On the logic side, read the density figures for what they compare. The symposium ratio works out at 9.3 times [22], and it is a comparison of two topologies, not two pitches. Second-generation SoIC is what adds face-to-face bonding on top of the face-to-back stacking the first generation supported [3], so the higher number belongs to a pair of dies joined active surface to active surface. If your part is a tower rather than a pair, the face-to-back column is yours. AMD, which has used the technique in volume since the first 3D V-Cache parts [5], cites roughly 15 times the interconnect density of conventional 2.5D microbump stacking [8], which is a third baseline again.
The pitch roadmap deserves the same arithmetic. Moving from 6 microns to 4.5 by 2029 [2] is a 1.78x gain in pads per unit area [24]. That is a real gain, but it falls short of a doubling.
The surface spec is the part worth sitting with, more than the roadmap numbers. There is no solder bump: the copper pads and the surrounding dielectric bond directly under heat and pressure [7]. The dielectric grabs on contact through van der Waals forces, so the polished surface can vary by no more than about 0.2 nanometres, with the copper pads sitting a few nanometres below it and swelling into contact when the stack is heated to 200 to 300 C [19]. One particle under a micron across holds the two faces apart and opens a gap spanning many pads at once [20]. The tool that decides your yield is the polisher, and the hardest part of copper-to-copper bonding happens before any copper touches.
