The technical case is a table of Intel's own measurements, and it deserves the treatment any vendor benchmark gets: 10 times the interconnect density of organic substrates and a 50% reduction in pattern distortion [8] are claims about Intel's line, Intel's dielectric stack, and Intel's design rules. Two things have to be true before those numbers describe your package. Your design has to be limited by substrate interconnect density rather than by thermals or die-to-die reach. And your supplier has to hold that process at the panel size that makes glass cheap in the first place.
Panel size is where the money actually is. In the emerging 510mm x 515mm format, more than 75% of panel area is usable for large die, against roughly 50% on a round 300mm wafer [10]. Call it about 1.5 times as much of each pass converting into product [2], before yield. "Before yield" is doing a lot of work in that sentence, and Absolics' early panel breakage is why [13].
The warpage argument is more careful than the marketing version. Glass cores can be tuned to a coefficient of thermal expansion of roughly 3 to 10 ppm per degree C against silicon's 2.6, which cuts warpage by about half compared with organic cores [9]. The bottom of that range sits within 0.4 ppm of silicon and the top is nearly four times it [4]. "Tuned" is load-bearing: the composition is chosen by whoever melts the glass, not selected late by the package designer.
The process engineering behind this is good work. Edge-coating has taken measured edge stress from 95 MPa to 49 MPa, a cut of about 48% [14][3], and dielectrics curing below 180C reduce thermal stress during build-up [14]. Through-glass vias have been demonstrated at six microns with aspect ratios past 15:1 [11], and Georgia Tech has run stacked glass at 220 GHz with 0.3 dB of loss [12]. What is still open is metallizing vias below 10 microns and holding nanometer-scale flatness across a half-meter panel [15]. Those two decide whether a panel line is a product or a demo.
Intel's demo vehicles are not vapour. It booted Windows on a glass-core substrate in early 2025 [16], and the package it showed in January carried about 1,716 mm2 of silicon, which the source calls roughly two full reticles, or about 858 mm2 each [19][5], over two 800-micron-class glass layers with 10 redistribution layers per side [19]. What changed is the business around the engineering: patent licensing, plus early-stage talks with Chinese cover-glass maker Lens Technology that DigiTimes reported in late July have produced no agreement [6][18]. Rahul Manepalli's "undeniable" [17] is a claim about physics. The date is a claim about schedule, and it lands seven years after the September 2023 announcement [1].
Korean industry reporting says Samsung samples have gone to AMD and Broadcom, and separately scores Samsung's overall glass maturity at 40 out of 100 [23]. Both can be true at once, and usually are. A sample is a request for feedback; a maturity score is a statement about how much process work is left. Packaging roadmaps get read as the first and priced as the second.
