Glass-core substrates spent a billion dollars to arrive at package-level reliability evaluation

Absolics originally planned mass production for the first half of 2024, and reported claims that AMD would adopt glass substrates for CPUs between 2025 and 2026 have come and gone unfulfilled.

The technical case for glass cores leans on numbers Intel published, including 10 times the interconnect density of organic substrates and a 50% reduction in pattern distortion.

Glass cores can be tuned to a thermal expansion coefficient of roughly 3 to 10 ppm per degree Celsius against silicon's 2.6, which cuts warpage by about half compared with organic cores.

Rectangular panels in the emerging 510mm x 515mm format use more than 75% of their area for large die, against roughly 50% for round 300mm wafers.

Through-glass vias have been demonstrated at six microns in diameter with aspect ratios beyond 15:1 at ECTC 2025.

Georgia Tech has shown stacked glass running at 220 GHz with 0.3 dB of loss.

Glass chips and cracks at the edges during drilling and dicing, and MIT Technology Review reported in March that early Absolics production runs broke hundreds of panels every couple of days during early testing.

Edge-coating work has cut measured edge stress from 95 MPa to 49 MPa, and low-temperature dielectrics that cure below 180C have been developed to reduce thermal stress during build-up.

Metallizing vias below 10 microns and holding nanometer-scale flatness across half-meter panels remain open manufacturing problems.

Intel demonstrated a working system booting Windows on a glass-core substrate in early 2025.

Rahul Manepalli, Intel's VP of module engineering, told MIT Technology Review that the benefits of glass cores are "undeniable" and that Intel wants "to be one of the first ones who do it."

At NEPCON Japan in January, Intel Foundry showed its first thick-core glass substrate with two EMIB bridge dies embedded directly in the glass: a 78mm x 77mm package with two 800-micron-class glass layers, 10 redistribution layers on each side, and around 1,716 mm2 of silicon on top, roughly two full reticles, with no micro-cracking reported in testing.

TrendForce places Intel's glass commercialization somewhere around 2030, alongside co-packaged optics prototypes built on glass at its Rio Rancho, New Mexico site.

Samsung Electro-Mechanics moved its glass program from advanced R&D into a business-execution unit in February and has been sampling from a pilot line at its Sejong plant since late 2024.

Intel's roughly 2030 deployment date falls about seven years after its September 2023 announcement.

A 510mm x 515mm panel converts about 1.5 times as much of its area into large-die product per pass as a round 300mm wafer.

The edge-coating result is a reduction in measured edge stress of about 48%.

The low end of the tunable glass CTE range sits within 0.4 ppm per degree C of silicon, while the high end is about 3.8 times silicon's value.

The 1,716 mm2 of silicon on Intel's NEPCON glass package works out to about 858 mm2 per reticle at two reticles.

Amkor, Intel's packaging partner on the optics work, put commercialization within three years at an industry event in Seoul in April.

DigiTimes reported in late July that Intel is in early-stage talks with Chinese cover-glass maker Lens Technology about a packaging partnership, with no solid agreement made to date.

Korean industry reporting says glass samples have gone to AMD and Broadcom, and puts Samsung's overall glass maturity at 40 out of 100.