SK hynix rules hybrid bonding out of HBM4E, leaving 55 microns to do the work

Run the arithmetic on the headroom JEDEC actually granted. The package ceiling went from 720 microns, which held through HBM3E, to 775 microns for HBM4 ^[6]. That is 55 microns ^[22] to absorb the step from 12-Hi to 16-Hi, or about 13.75 microns per added die ^[23], and each of those microns has to cover the die, the gap beneath it, and whatever fills the gap. Lee's own number for 16-Hi core dies, around 50 microns ^[4], does not close either: sixteen of them is 800 microns ^[24], past the ceiling before a base die or a single joint is counted. So the shipping core die sits under the round number in the deck, or the base and top dies give back the difference.

The heat side moves faster than the thickness side. Pin speeds have gone from 1 Gbps in early HBM to 8 Gbps in HBM4 ^[9], an eightfold rise into the same footprint, against a thermal burden SK hynix puts at 2.2 times across the generations shown ^[10][26]. The stack that has to carry that heat out is getting proportionally more oxide as dies thin, and oxide is a poor conductor next to silicon ^[8]. MR-MUF places every die by pick-and-place and joins them in one reflow ^[11], and Lee named the real difficulty of 16-Hi as filling gaps that have halved while keeping sub-50-micron dies flat ^[11][4].

Copper bonding would buy back room. Removing micro-bumps lets core dies grow up to 24% thicker at 20-Hi, cuts thermal resistance by roughly 35% against MR-MUF at that height, and takes bump pitch below 18 microns against 30 today ^[18], at least 40% finer ^[28]. It is also still a research item above 20 layers, with no product named yet ^[16]. "This is a very simple process, but in reality it's really challenging," Lee said of stacking 16 and 20 layers that way ^[30]. None of it is urgent while the ceiling keeps moving: industry discussion of 825 to 900 microns for 20-Hi ^[13] would add another 50 to 125 microns of relief ^[27]. The hedge is priced to match, one inline system pairing Applied Materials and Besi tools at about 20 billion won, or $15 million, per industry sources in March ^[14]. Counterpoint Research expects full-scale hybrid bonding at HBM5 around 2029 to 2030 ^[15], three to four years past the Hot Chips talk ^[29].

The cooling story carries the harder commercial term. iHBM embeds thermally conductive, electrically insulating blocks in the base die's die-to-die PHY region, where power density peaks, for a claimed reduction in thermal resistance of more than 30% ^[20]. Lee's constraint is that the blocks cannot be applied to any HBM generation already in design ^[5]. That is a gate on the design calendar, not a lead time. And the comparison set is unaudited: Samsung's Heat Path Block routes heat through dedicated pillars, Micron redesigns the base-die circuit for a claimed 20%-plus energy efficiency gain, and all three are vendor figures from vendor benchmarks ^[21]. Anyone specifying HBM4E now has the packaging answer already: mass reflow, 775 microns, no heat blocks.