Micron's own numbers say the DRAM squeeze is an allocation problem, not a cycle

Micron said that in a two-GPU package, memory accounts for around 90% of the silicon, roughly eight times the area of the GPU dies.

HBM already sells for about five times the price of DDR5 per bit, so each wafer a maker moves to it removes a disproportionate share of commodity memory from the market.

A mainstream 32GB DDR5-6000 kit sold for around $392 this month, up from $110 to $140 a year earlier, and 128GB of DDR5 passed $3,399, a 500% rise over 12 months, with European prices up 345% since September last year.

In February, HP told investors that DRAM now makes up 35% of its PC build cost, up from 15% to 18% a quarter earlier.

Gartner expects PC shipments to fall more than 10% in 2026.

Micron's presentation put compute performance scaling at roughly three times every two years and HBM bandwidth at under two times, a divergence Sreeramaneni summarized by saying "the memory wall is still present, and, in fact, maybe getting worse."

HBM4 doubles the host interface to 2,048 I/Os, and Micron's parts run above 11 Gb/s per pin for more than 2.8 TB/s per stack, beyond the 8 Gb/s and 2 TB/s baseline in JEDEC's HBM4 standard.

Each of those bandwidth gains comes from more parallelism, which enlarges the die again and widens the silicon ratio.

Sreeramaneni said there is "a good path to 16 layers of DRAM," but "after 16, there's still a lot of work to be done."

SK hynix used its own Hot Chips talk to describe a 775-micron total-thickness ceiling that caps stacking until the industry adopts hybrid bonding, which SK hynix does not expect before HBM5.

Micron's HBM4E, due around 2027, moves the logic base die to a TSMC foundry process, part of a wider shift toward customization as AI workloads fragment.

The base die runs hottest because it sits at the bottom of the stack doing the highest-speed interface work while the heatsink sits at the top, and every layer added between them raises thermal resistance; Sreeramaneni said Micron is now "architecting solutions around thermals rather than the other way around."

Micron highlighted that Meta's Llama 3 paper attributed 17.2% of unexpected interruptions during a 54-day run across 16,384 H100 GPUs to HBM3 memory, the second-largest cause behind failed GPUs, a reliability burden that scales with the amount of HBM in each package.

HBM3E delivers about 32 times the per-die bandwidth of DDR5 for roughly three times the wafer area, which is about eleven times the bandwidth per unit of wafer area.

Compounding the three reported quarterly contract price increases gives a cumulative rise of roughly 3.4 to 3.8 times over three quarters.

With compute scaling about 3x every two years and HBM bandwidth under 2x, the gap widens by at least 1.5x every two years, roughly 3.4x over six years if both rates hold.

At five times the DDR5 price per bit and three times the wafer area for the same capacity, a wafer converted from commodity DRAM to HBM produces about a third of the bits at five times the price, or roughly 1.67 times the revenue per wafer.

The contract price surge eased to 13% to 18% in the third quarter, which Tom's Hardware attributes to consumer electronics makers reaching the ceiling of what they could pass on rather than to supply improving.