Micron's own numbers say the DRAM squeeze is an allocation problem, not a cycle

The arithmetic that decides whether this reverses sits on the supplier's side of the table. HBM sells for about five times DDR5 per bit ^[6], and a wafer converted to it yields roughly a third of the bits, which works out to about 1.67 times the revenue per wafer ^[1]. That is the entire allocation decision, and it does not unwind because a retail memory kit got expensive.

Per unit of bandwidth, HBM is the efficient product, which is why calling the silicon ratio an overhead understates it. A single HBM3E die feeds 256 GB/s where one DDR5 die supplies about 8 GB/s ^[3], so 32 times the bandwidth for three times the area, or roughly eleven times the bandwidth per unit of wafer ^[2]. AI buyers are paying for bandwidth and PC buyers are paying for capacity, out of one wafer supply, and capacity loses.

The widening is mechanical rather than strategic. Raghu Sreeramaneni said the three-times figure traces to an HBM3E-against-DDR5 comparison and grows as pin speeds, bank counts, stack heights and die sizes climb ^[4]. HBM4 doubles the host interface to 2,048 I/Os, and Micron's parts run above 11 Gb/s per pin for more than 2.8 TB/s per stack, past JEDEC's 8 Gb/s and 2 TB/s baseline ^[13]. Each of those gains is bought with parallelism, and parallelism is die area ^[14]. Closing the gap would cost performance, and Micron says it will not do that ^[20].

What the extra silicon buys is not keeping pace with what needs it. Micron's presentation put compute scaling at roughly three times every two years against HBM bandwidth under two times ^[12]. Compounded, the shortfall grows by at least half again every two years, about 3.4 times over six years if both curves hold ^[3]. Sreeramaneni's own summary was that the memory wall is "maybe getting worse" ^[12].

On the buy side the compounding has already happened. The third quarter's step down to 13% to 18% ^[8] still stacks on what came before: three quarters together multiply out to between roughly 3.4 and 3.8 times ^[4]. Tom's Hardware reports the deceleration came from consumer electronics makers reaching the ceiling of what they could pass on rather than from supply improving ^[8]. HP told investors in February that DRAM had gone from 15% to 18% of PC build cost to 35% in a single quarter ^[10], and Gartner expects PC shipments to fall more than 10% in 2026 ^[11].

The way out is more layers per stack instead of more area per layer, and that route is currently blocked. SK hynix used its own Hot Chips talk to describe a 775-micron total-thickness ceiling that caps stacking until the industry adopts hybrid bonding, which it does not expect before HBM5 ^[16]. Sreeramaneni sees a good path to 16 DRAM layers and a lot of work still to be done past that ^[15]. Until one of those two things moves, anyone treating the memory line as cyclical is budgeting against a ratio that Micron's own architect describes as going the wrong way.