Samsung's glass-carrier cleaning orders rise fivefold in two years

Glass carriers get consumed by thinning, not by DRAM wafer output, so the two planning numbers do not scale together. Samsung's HBM wafer starts are put at about 250,000 a month next year against roughly 180,000 this year ^[10], an extra 70,000 a month ^[2]. The cleaning order goes up by a factor of 2.5 ^[2]. Divide one by the other and next year's plan buys about 1.8 times as much carrier cleaning per wafer start ^[3].

That gap is mix. The HBM4 series is seen at roughly 80 per cent of shipments next year against around 40 per cent this year ^[11]. If that split carries across to wafer starts, HBM4-series wafers go from about 72,000 a month to about 200,000, a factor of 2.78 ^[4]. The 2.5-fold carrier order comes in roughly a tenth under that ^[5]. Shipments and wafer starts are different measures, so 2.78 is an implied figure rather than a reported one.

A carrier is a support temporarily attached to the underside of an HBM DRAM wafer to keep it from bending or cracking while it is ground thin and drilled ^[4]. HBM4 and HBM4E are high-stack parts of 12 layers or more ^[6], and because the dies have to fit inside a limited package thickness, thinning and warpage control get harder as the stack count rises ^[5]. Carrier demand follows stack count.

What the cleaning contract fixes is service capacity for next year. Samsung has not published the volumes; they come from semiconductor industry sources cited by Seoul Economic Daily ^[2]. A larger cleaning order can mean more good output. It can also mean shorter carrier life: at 12 layers and above a sheet may survive fewer cycles, and more wafers may crack on the way through. In that case 50,000 sheets a month yields no more finished stacks than 30,000 would have. The check arrives next year. If HBM4-series shipments fail to double while the cleaning volume holds at 50,000, the extra sheets went to attrition. The officials quoted hedged in that direction themselves. Even allowing for reuse after cleaning and for usage varying by process and yield, they said, the 2.5-fold step points to HBM4 and HBM4E output at least doubling ^[7].

I would read the order as a capacity plan, not as evidence of sold volume. It does commit named capacity: HBM4 entered mass-production shipments in February on sixth-generation 1c DRAM with a base die built on a 4-nanometer process ^[8], and 12-layer HBM4E samples went to customers including Nvidia in May ^[9]. An 80 per cent HBM4 mix ^[11] books 1c wafers and 4-nanometer base dies into stacks a year ahead of the revenue. "As Samsung expands HBM output, it appears to be placing HBM4, a high-margin product, at the center," an industry official said ^[12].