Intel dates Diamond Rapids: 256 P-cores, 1.28 GB of cache, and 2027 to plan around

Divide 1.28 GB of last-level cache by 256 cores and you get roughly 5 MB of shared L3 per core ^[14]. That cache sits on four base tiles built on Intel 3-T, so about 320 MB rides on each one ^[16]. The core count is arithmetic as well: four Compute Building Blocks, four core chiplets in each, 16 P-cores per chiplet ^[2]. The headline 256 therefore describes the fully populated arrangement, all 16 core chiplets present ^[15], which is a ceiling and not a shipping configuration.

What is absent matters more for modeling than what is present. Intel did not describe the Panther Cove core at its Hot Chips 2026 presentation, and Tom's Hardware expects at least one further technical session before the parts arrive ^[10]. So the 2027 model you can build now has socket density, cache per core, 16 memory channels ^[5] and a 128-lane I/O budget ^[11], and nothing about per-core throughput. If your software bill counts cores, that asymmetry is workable, because the licence does not care about instructions per clock. If you are computing a consolidation ratio against installed hardware, you are still guessing.

The interconnect change is the part that carries risk rather than marketing. Inside each CBB, Foveros Direct 3D bonds the core chiplets to the base tile across a 3D crossbar, as on Clearwater Forest ^[3]. Outside the CBB, the connection to two centralized fabric hub tiles is UCIe-S over copper, and every CBB reaches both hubs ^[7][8]. Intel is not using EMIB here, the bridge it has deployed broadly in past products ^[7]. A seam that used to be proprietary silicon is now a standard interface on Intel's own flagship socket.

The floorplan is inverted relative to Granite Rapids, with memory and I/O pulled into the middle and the cores pushed to the edges, closer to how AMD arranges a server die ^[9]. Tom's Hardware reads that as a thermal improvement, since the hottest, highest-clocked silicon no longer sits in the centre the way it does on Granite Rapids-AP ^[19]. That is the publisher's inference. Intel has not put a number on it.

The only performance figures on the table are node figures: 18A-P is said to deliver 9% more performance than 18A at peak, or 18% lower power at matched performance, and it entered risk production in June ^[4]. Those describe a process, not a core, and they are not additive with anything else disclosed.

For anyone doing memory sizing, the channel count is the more consequential number. Sixteen channels is a third more than Granite Rapids managed ^[18], and MRDIMMs at 12,800 MT/s run 60% above the 8,000 MT/s DDR5 ceiling on the same platform ^[17][5]. Feeding 256 cores is the harder engineering problem than counting them, and this is the first P-core Xeon where the memory side has been widened to match the core side.

Also on the die, if your workload touches them: QAT and IAA complexes hang off the I/O fabric ^[12], and the cores carry AVX 10.2 ^[13].