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Intel's Hot Chips disclosure gives capacity and licensing planners real numbers for 2027, but leaves out the one figure that would let anyone model per-core performance.
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Divide 1.28 GB of last-level cache by 256 cores and you get roughly 5 MB of shared L3 per core [1]. That cache sits on four base tiles built on Intel 3-T, so about 320 MB rides on each one [3]. The core count is arithmetic as well: four Compute Building Blocks, four core chiplets in each, 16 P-cores per chiplet [2]. The headline 256 therefore describes the fully populated arrangement, all 16 core chiplets present [2], which is a ceiling and not a shipping configuration.
What is absent matters more for modeling than what is present. Intel did not describe the Panther Cove core at its Hot Chips 2026 presentation, and Tom's Hardware expects at least one further technical session before the parts arrive [9]. So the 2027 model you can build now has socket density, cache per core, 16 memory channels [11] and a 128-lane I/O budget [12], and nothing about per-core throughput. If your software bill counts cores, that asymmetry is workable, because the licence does not care about instructions per clock. If you are computing a consolidation ratio against installed hardware, you are still guessing.
The interconnect change is the part that carries risk rather than marketing. Inside each CBB, Foveros Direct 3D bonds the core chiplets to the base tile across a 3D crossbar, as on Clearwater Forest [4]. Outside the CBB, the connection to two centralized fabric hub tiles is UCIe-S over copper, and every CBB reaches both hubs [5][6]. Intel is not using EMIB here, the bridge it has deployed broadly in past products [5]. A seam that used to be proprietary silicon is now a standard interface on Intel's own flagship socket.
The floorplan is inverted relative to Granite Rapids, with memory and I/O pulled into the middle and the cores pushed to the edges, closer to how AMD arranges a server die [7]. Tom's Hardware reads that as a thermal improvement, since the hottest, highest-clocked silicon no longer sits in the centre the way it does on Granite Rapids-AP [8]. That is the publisher's inference. Intel has not put a number on it.
The only performance figures on the table are node figures: 18A-P is said to deliver 9% more performance than 18A at peak, or 18% lower power at matched performance, and it entered risk production in June [10]. Those describe a process, not a core, and they are not additive with anything else disclosed.
For anyone doing memory sizing, the channel count is the more consequential number. Sixteen channels is a third more than Granite Rapids managed [5], and MRDIMMs at 12,800 MT/s run 60% above the 8,000 MT/s DDR5 ceiling on the same platform [4][11]. Feeding 256 cores is the harder engineering problem than counting them, and this is the first P-core Xeon where the memory side has been widened to match the core side.
Also on the die, if your workload touches them: QAT and IAA complexes hang off the I/O fabric [13], and the cores carry AVX 10.2 [14].
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Intel has detailed next-gen Xeon 7, codenamed Diamond Rapids, with up to 256 P-cores and 1.28 GB of last-level cache, set to release in the data center in 2027.
Diamond Rapids is built with four Compute Building Blocks (CBBs), each of which includes four core chiplets housing 16 P-cores each; each core chiplet can hold up to 16 cores and up to four chiplets can live in a CBB.
Cores have private L2 within each chiplet and share an L3 cache located on the base tile; chiplets connect to the base tile via a 3D crossbar, packaged with Foveros Direct 3D, as seen with Xeon 6+ 'Clearwater Forest'.
Intel's enhanced 18A-P node is said to increase performance by 9% compared to 18A at peak performance, or operate at 18% lower power at iso-performance; Intel announced in June that 18A-P had entered risk production.
Diamond Rapids has 16-channel memory supporting up to 8,000 MT/s with DDR5 and up to 12,800 MT/s with MRDIMMs; Granite Rapids topped out at 12 channels.
A full Diamond Rapids SoC includes four base tiles built on Intel 3-T, two fabric hub tiles built on Intel 3, and 16 core chiplets built on Intel 18A-P.
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Evidence-backed comparisons of source perspectives and observed adoption signals. Read the methodology
Which Builder, Operator, and Investor concerns the observed source mix emphasized—not a truth score.
Evidence, demonstrated adoption, hype gap, incentives, and confidence are assessed independently, each on its own current evidence. How these are measured.
Detailed first-party disclosure, single outlet, no measurements
The specification set is unusually concrete — tile counts and process nodes, cache topology, packaging choices, memory channels and rates, lane counts — and is drawn directly from an Intel conference session including Q&A on UCIe-S versus UCIe-A. But every number is vendor-stated and relayed by a single publisher, with no independent testing, no second account of the session, and the headline gap that Panther Cove core details were withheld, so per-core performance cannot be checked at all.
Pre-launch disclosure; nothing shipping before 2027
There is no deployment to measure. The only observable milestones are a conference architecture disclosure and Intel's statement that the 18A-P node entered risk production in June; the product itself is stated for 2027 with no named customers, SKUs, platform partners, sampling or volume timing reported.
Slightly overstated: big headline numbers, unmeasurable performance
The coverage is mostly restrained and spec-led, and it explicitly flags that Panther Cove was not detailed. The overstatement is mild and comes from framing: 256 cores and 1.28 GB of cache are maximum-configuration figures presented as headline capability, thermal improvement is asserted as likely from floorplan reasoning alone, and Intel's 18A-P performance and power deltas are repeated without independent validation for a part that is still roughly a year and a half from release.
Vendor roadmap disclosure relayed by enthusiast press
The primary information source is Intel presenting its own future product and its own process node, a setting where the vendor has a clear interest in demonstrating that 18A-P and the Xeon roadmap are on track; the node figures and the 'made the most sense for Diamond Rapids' framing of the UCIe-S choice are both Intel's characterizations. The relaying publisher is hardware enthusiast media whose interest lies in early spec disclosures, and the article carries no disclosed sponsorship or commercial relationship in the supplied material.
Moderate: specifics are solid, single-sourced and unverified
Confidence is limited by structure rather than plausibility. The architectural and platform specifics are internally consistent and detailed enough to plan against, and derived ratios follow arithmetically from stated figures. But there is one publisher, one primary (vendor) source, no measurements, an explicitly withheld core architecture, and a release date far enough out that specifications can still change before 2027.
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