Intel skipped Foveros on Wildcat Lake because the open link was the cheaper part

Without a base die to carry the link, the interface logic has to sit on the product dies themselves, and on Wildcat Lake that means 18A area, the most expensive silicon on the package ^[7][9]. Intel's own figure for the overhead is an interconnect 70% larger than the one on Panther Lake, and the company still says the trade paid off on cost ^[6]. Foveros was on the shelf and would have cut both the area and the power, and lead engineer Lance Hacking told the conference it was not an option for a part in this class ^[1][3][9].

The invoice got settled in features. On the compute die, four Xe cores became two, the dedicated ray tracing accelerator went away, the NPU dropped from three tiles to one, and the memory subsystem came down to a 64-bit bus with lower peak speeds and capacity ^[10]. That is half the graphics and two thirds of the NPU gone ^[11]. The display engine went to three pipelines and HBR3 instead of UHBR20, which still drives 4K60 on three external panels ^[14].

How little of UCIe Intel actually wanted shows up in the link rate. UCIe 3.0 reaches 64 GT/s. Wildcat Lake runs its link at 8 ^[15]. That is one eighth of what the specification allows ^[16], and the reason is that a slow link produces fewer bit errors, which let Intel strip out some bit-correction logic and bank that area as well ^[17]. The standard is being used as a packaging discount, not for its headline bandwidth.

Packetized traffic is what makes the display hard. Signals that would have stayed on one die now have to cross a link, and power, not space, was the primary worry ^[18]. Intel names idle systems without panel self-refresh as its biggest power concern and answers it with a buffer that holds panel refreshes, placed ahead of the UCIe link and sitting alongside the usual display buffer between the memory controller and the display engine ^[19].

The inversion worth noting is the IP, not the interconnect. Value parts normally recycle N-1 silicon, trimmed at the edges for yield ^[8]. This one puts Intel's newest and dearest compute IP in the cheap slot and pays for the privilege by cutting almost everything around it. That arrangement only closed because an open link was cheaper than a packaging technology Intel already owns, four years after the specification appeared and after both Intel and AMD spent those years shipping their own fabrics in preference to it ^[4][5][12].