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Intel skipped Foveros on Wildcat Lake because the open link was the cheaper part
At Hot Chips 2026 Intel said an open die-to-die link, not advanced packaging, is what made its entry-level 18A chip possible. The bill came to 70% more interconnect area.
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What happened
- Intel told Hot Chips 2026 that Wildcat Lake's two dies talk over UCIe, and that the open standard is what let the part exist at all.
- The engineering choice was monolithic silicon or a basic low-cost multi-chip package; Intel's own Foveros packaging was ruled out for a part at this price.
- Intel reclaimed 38% of the compute die and 15% of the I/O die to pay for the link's footprint.
Why it matters
- cost Deleting the camera PHY moves that line item off Intel's die and onto the OEM bill of materials, so the buyer of a cheap laptop pays for the interconnect in a controller Intel no longer supplies.
- precedent If the thinnest-margin part in the line can absorb an open link's area and power penalty, the argument that die-to-die standards only pencil out on expensive packaging loses its cost defence.
- constraint Banking area by stripping bit-correction logic ties the platform to the slow link; a faster rate later is a new die, not a firmware setting.
- exposure Idle battery life is where this design can disappoint in the field, because the fix for display traffic crossing the link is a buffer rather than a shorter path.
Without a base die to carry the link, the interface logic has to sit on the product dies themselves, and on Wildcat Lake that means 18A area, the most expensive silicon on the package [8][4]. Intel's own figure for the overhead is an interconnect 70% larger than the one on Panther Lake, and the company still says the trade paid off on cost [3]. Foveros was on the shelf and would have cut both the area and the power, and lead engineer Lance Hacking told the conference it was not an option for a part in this class [5][2][4].
The invoice got settled in features. On the compute die, four Xe cores became two, the dedicated ray tracing accelerator went away, the NPU dropped from three tiles to one, and the memory subsystem came down to a 64-bit bus with lower peak speeds and capacity [10]. That is half the graphics and two thirds of the NPU gone [18]. The display engine went to three pipelines and HBR3 instead of UHBR20, which still drives 4K60 on three external panels [12].
How little of UCIe Intel actually wanted shows up in the link rate. UCIe 3.0 reaches 64 GT/s. Wildcat Lake runs its link at 8 [13]. That is one eighth of what the specification allows [20], and the reason is that a slow link produces fewer bit errors, which let Intel strip out some bit-correction logic and bank that area as well [14]. The standard is being used as a packaging discount, not for its headline bandwidth.
Packetized traffic is what makes the display hard. Signals that would have stayed on one die now have to cross a link, and power, not space, was the primary worry [15]. Intel names idle systems without panel self-refresh as its biggest power concern and answers it with a buffer that holds panel refreshes, placed ahead of the UCIe link and sitting alongside the usual display buffer between the memory controller and the display engine [16].
The inversion worth noting is the IP, not the interconnect. Value parts normally recycle N-1 silicon, trimmed at the edges for yield [9]. This one puts Intel's newest and dearest compute IP in the cheap slot and pays for the privilege by cutting almost everything around it. That arrangement only closed because an open link was cheaper than a packaging technology Intel already owns, four years after the specification appeared and after both Intel and AMD spent those years shipping their own fabrics in preference to it [6][7][19].
What to watch
- Whether Intel's next value part reuses this same N6 I/O die or sources one from an outside vendor now that the interface is standard.
- Whether AMD ships a UCIe die-to-die link in a mainstream client part rather than Infinity Fabric.
- Whether independent reviewers can measure the idle power penalty the panel refresh buffer was built to hide.
Clarity's read
What the record supports and how the coverage leans. The claims behind it follow.
Reality
- Evidence58
- Adoption28
- Hype gap+12
- Incentives72
- Confidence45
Claim ledger
Ranked by verification strength, evidence, and original report placement.
- [1]
In Wildcat Lake, Intel leveraged UCIe to reduce cost, and it was a key technology that allowed Wildcat Lake to exist in the first place.
- [2]
Intel had a choice between a monolithic design and a basic, low-cost Multi-Chip Package; Intel has Foveros for advanced 2.5D and 3D packaging, but for a budget part like Wildcat Lake that was not an option.
- [3]
With UCIe, Wildcat Lake's interconnect is 70% larger than the one on Panther Lake, and Intel says the change was worth it from a cost perspective.
- [4]
Advanced packaging allows designers to spend less die space on interconnects and use less power; without a base die for interconnect communication, UCIe represents a large increase in die area.
- [5]
Intel detailed Wildcat Lake at Hot Chips 2026, in a presentation opened by Lance Hacking, lead engineer on the product.
- [6]
The UCIe specification first debuted in 2022, around the same time planning for Wildcat Lake began.
- [7]
Both AMD and Intel have rallied behind UCIe as an open interconnect standard, though they have primarily relied on their own chiplet communication technology, such as AMD's Infinity Fabric.
- [8]
Wildcat Lake places 18A at the centre of compute, with an N6 process handling the I/O die.
- [9]
Budget parts usually involve an N-1 design that reuses older IP and trims at the edges for yield; Wildcat Lake instead applies Intel's latest, most advanced and most expensive compute IP to the budget domain.
- [10]
On the compute die Intel cut four Xe cores to two, dropped the dedicated ray tracing accelerator, reduced the NPU from three tiles to a single tile, and downgraded the memory subsystem to a 64-bit bus with lower maximum speeds and lower capacity.
- [11]
Trimming the compute die let Intel claw back 38% of its die space, and cuts to the I/O die reclaimed 15% of its area by removing the camera PHY, reducing PCIe and USB support and slimming the audio engine.
- [12]
Intel uses three display pipelines instead of four and opted for HBR3 rather than UHBR20, which still provides 4K60 and can drive three external displays.
- [13]
UCIe 3.0 is capable of data rates up to 64 GT/s, but Intel capped the transfer rate in Wildcat Lake at 8 GT/s, which still supports mainstream PCIe 4 SSDs and 4K60 external displays.
- [14]
Running the link at a lower data rate reduces bit-rate errors and therefore allowed Intel to remove some bit-correction systems.
- [15]
Outside of die space, power was the primary concern with using UCIe; the die-to-die link is packetized, which led to a challenging design point, particularly around the display, and battery life matters for a budget part aimed at lighter workloads.
- [16]
Intel says idle systems without panel self-refresh were the biggest power concern because display signals must cross the UCIe connection, and it built a buffer to hold panel refreshes while the system is idle, placed before the UCIe link as an additional output buffer alongside the usual display buffer between the memory controller and display engine.
- [17]
The camera was completely removed from the I/O die, placing the onus on OEMs to integrate their own controllers.
- [18]
The Xe core count fell by half and the NPU tile count fell by two thirds.
- [19]
Hot Chips 2026 is four years after the 2022 debut of the UCIe specification.
- [20]
Wildcat Lake's 8 GT/s link runs at one eighth of the peak rate UCIe 3.0 permits.
Sources
1 independent publisher whose own reporting we read for this story.
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