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Samsung told Hot Chips 2026 it intends to hollow out the accelerator by relocating its non-compute blocks into a 4nm HBM base die. The stated endpoint of that plan is a memory stack with no interposer under it.
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Start with the floorplan arithmetic, because that is the part you can check. An 11 by 12.8mm HBM4 base die is 140.8 mm2 of silicon [1]. The conventional PHY on it occupies more than 8 by 4mm, so at least 32 mm2, roughly 23% of the die [11][2]. The custom-HBM die-to-die block Samsung proposes in its place measures about 8.5 by 1.5mm, or 12.75 mm2, at least 60% smaller [11][3]. Channel depth drops from 5.5mm to 2mm, another 64% [11][5]. The reason this matters on the compute side is that the mating interface on the XPU shrinks with it, so the accelerator gets silicon back too [12].
Then the controller. Sangwook Han of Samsung's DRAM design team put memory controllers at 5 to 10% of XPU area, and estimated that refilling that space with compute could return 10 to 20% more performance [15]. Read the ratio: two points of performance for every point of area handed back [4]. That holds only if the part is compute-bound at the margin, if the freed area is contiguous enough to hold real execution units rather than routing, and if moving the controller next to the DRAM does not add latency that eats the gain. Those conditions are not given; they are what has to hold for the number to transfer to your part.
The repair scheme is the quietly good piece of engineering here. Today a single defective cell can cost an entire spare row or column; with the controller on the base die, failed core-die addresses can be redirected into base-die SRAM instead [16]. That turns a coarse repair granularity into a fine one, which is a yield argument, not a bandwidth one.
The thermal claim needs the same treatment. Concentrating the same interface power into less silicon raises power density and creates hotspots [13]. Samsung's answer is a Heat Path Block over more than half the PHY area, which it says cuts peak temperature by more than 35% [14]. That is a number about Samsung's power map, its floorplan, and its package stack. To transfer, you would need comparable interface power in comparable area and a lid-to-coldplate path of similar thermal resistance. It also matters whether 35% is measured against ambient or as an absolute reading, which the presentation summary does not say.
The part that dates your packaging assumptions is the endpoint. zHBM puts the processor directly beneath the DRAM stack and removes the conventional 2.5D interposer link between them [2]. Samsung's stated reason for going down this path is that the base die moved to a 4nm logic process at HBM4, primarily for power and area, which left it capable of doing more than interfacing [4][17]. Interposer and reticle limits are named as the walls the accelerators are hitting [10]. So the fix Samsung is pursuing is removing the interposer entirely, not enlarging it. Geometrically, that also puts DRAM on the far side of the hottest die from the substrate, and the material available here stops partway through phase 2, before that gets addressed.
One more thing worth pricing: cHBM keeps the standard DRAM stack but customises the logic beneath it for a specific accelerator [9]. A memory part tuned to one customer's controller becomes hard to second-source in a hurry.
Ranked by verification strength, evidence, and original report placement.
Samsung detailed a three-phase HBM roadmap at Hot Chips 2026, presented by Sangwook Han of the company's DRAM design team, who identified the base die as the key enabler of the evolution.
In conventional HBM, the base die was fabricated on the same DRAM process node as the core dies stacked above it.
Starting with HBM4, Samsung moved the HBM base die to a 4nm logic process, primarily to reduce power draw and minimise die area, which also gave it a more capable piece of silicon.
The current HBM4 stack has roughly 1 to 5 TB/s of bandwidth obtained through 1,000 to 2,000 I/Os running at about 8 to 16 Gbps each.
HBM4 doubled the data I/O count from 1,024 to 2,048 DQs.
TSV signalling speed is difficult to increase, so HBM generations have added more TSVs, which consumes area and forces tighter TSV pitches.
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Evidence-backed comparisons of source perspectives and observed adoption signals. Read the methodology
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One talk, one write-up, Samsung's own numbers
The technical detail is unusually concrete for a roadmap story — die dimensions, DQ counts, bandwidth envelopes — and concrete enough that the area and percentage reductions can be recomputed and confirmed. What it isn't is corroborated: Tom's Hardware is the only account, Samsung is the only measurer, and the write-up breaks off inside the zHBM section, leaving the most consequential phase the least documented part of the story.
One shipping step, two slideware phases
Exactly one item on this roadmap exists in silicon: the HBM4 base die built on 4nm logic. Custom HBM, advanced HBM and zHBM are intentions with no generation, no schedule and — most tellingly — no accelerator partner, even though customising base-die logic for a specific XPU cannot happen without one. The absence of a named co-designer is the loudest thing in the story.
Vendor upside up front, unknowns further down
The headline arithmetic — hand back 5 to 10% of the die, collect 10 to 20% more performance — is Samsung's estimate and travels without a workload attached, while 'ultimate solution' language surrounds an architecture whose description here is literally incomplete. The gap stays moderate rather than wide because Tom's Hardware keeps the attribution visible throughout and prints the hotspot problem alongside the area win instead of after it.
The memory vendor measuring its own land grab
Samsung is arguing that work now done on the accelerator belongs under the DRAM it sells, and every quantity that makes the argument attractive was produced by Samsung. The presenter is from its DRAM design team; the venue rewards ambitious architecture. Note also which number never appears: how much accelerator power moves with the controller, in a story whose own premise is that total HBM power keeps climbing.
Sure what was said, unsure what it yields
We can be fairly firm that Samsung said these things and that the geometry is internally consistent. We can be firm about very little else: no second reporting of the session, no independent measurement, no timeline, and a truncated description of the phase that matters most. Confidence here attaches to the statement, not to the outcome.