Intel's Crescent Island bets 480GB of LPDDR5X and 350W beats paying for a liquid retrofit

Add the per-core figures up and the design intent stops being a positioning statement. Thirty-two Xe Cores carrying 1MB of general register file each comes to 32MB of register space ^[12][3][19], the same amount as the shared L2 on the same die ^[4], with a further 16MB sitting in per-core L1 and shared local memory ^[5][20]. Intel says Xe3 already reworked the cache hierarchy to improve utilisation and cut register spills, and that Xe3P refines it further ^[2]. That is a large SRAM budget for an inference part, and it is the sort of budget you spend when the memory behind it is LPDDR5X rather than the HBM4 pools on Nvidia's Rubin and AMD's MI455X ^[1][11].

The matrix engines point the same way. Xe3P's XMX systolic arrays are 16 stages deep against four in Xe2 and Xe3, a fourfold increase ^[13][23], which on Intel's own description means each pass works through larger chunks of a matrix at once ^[13]. Deeper arrays and fatter register files buy the same thing: more arithmetic per byte pulled across the bus.

What the Hot Chips material does not contain, at least as reported by Tom's Hardware, is a memory bandwidth number ^[17]. Everything else is there in unusual detail, including a level of systolic-array description Tom's Hardware notes Nvidia does not offer for its Tensor Cores ^[24]. The workload Intel chose to highlight is the tell: mixture-of-experts models paired with speculative decoding ^[7], where a lightweight drafter proposes tokens the main model accepts or rejects, extracting useful work from compute that would otherwise idle ^[8]. Tom's Hardware notes that more aggressive drafting demands more compute ^[9]. Those are precisely the recipes that convert bandwidth-starved decode into batched matrix work. A part with plenty of resident capacity and deep XMX pipes is well matched to that regime and poorly matched to the one it replaced.

The FP64 decision is the other giveaway. Sixty-four FP64 FMA units per Xe Core is 2,048 across the die ^[12][6][21], full rate, on a chip Intel concedes is aimed at workloads where FP64 barely appears ^[6]. Ray tracing hardware was cut to preserve die area for compute ^[14], so the double-precision silicon survived a real trade. It is there to make the card biddable into converged HPC and AI procurements ^[6], alongside the ECC and parity coverage across the die that any data centre buyer will insist on ^[15].

Tom's Hardware frames the larger caches and deeper engines as a hunt for maximum AI FLOPS per watt ^[18]. The metric that actually follows from the parts list is different: 480GB inside a 350W envelope is roughly 1.37GB of resident model per watt ^[22], in a slot that needs no facility work ^[1]. For an operator with air-cooled halls, the comparison is not against Rubin's peak throughput but against the cost of plumbing a room that has no loop in it. Intel has built a card that only wins that comparison, and only if the bandwidth number, when it appears, is good enough to keep 480GB busy.