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CXMT's two 50 per cent claims multiply to 2.25 times the bits per wafer
Changxin Memory says its fifth-generation platform is in mass production at 11.95nm with at least 50 per cent more dies per wafer. Both of the figures that would let a buyer price it come from the company.
The Investor · Invest desk
What happened
- CXMT said on Sunday that it had moved its new-generation technology platform into mass production, narrowing the manufacturing-node advantage held by Samsung Electronics and SK Hynix.
- The company said the fifth-generation G5 platform lifts the number of dies produced per wafer by at least 50 per cent over the previous generation while holding energy efficiency and cost control.
- CXMT put the node at 11.95nm, reached with quadruple exposure, and said that brings it close to the world's most advanced mass production memory platforms.
- It also showed two mass-produced LPDDR5X parts built on G5, each carrying 24 gigabits, half again the capacity of the previous generation of similar mobile DRAM products.
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Why it matters
- cost Denser wafers cut cost where memory makers compete hardest, and if CXMT's figures hold at volume the incumbents' gross margin absorbs the pressure before their list prices do.
- decision Handset makers now have a candidate second source for high-capacity mobile DRAM, and whether it becomes a real one sits on their qualification calendars, not CXMT's.
- exposure Anyone holding Samsung or SK Hynix on the strength of a node lead is exposed to a density claim that so far only the supplier has measured.
The two 50 per cent figures multiply. If the die-count gain and the capacity gain sit on one baseline and one wafer size, bits per wafer come out 2.25 times higher than the generation before [7].
Whether they sit on one baseline is the open question. CXMT gave the die-count gain against its previous technology platform, and the capacity gain against the previous generation of similar products [3][6]. The statement does not reconcile the two. The product figure is the firmer of them: a 24-gigabit die that is half again the capacity of its predecessor implies a 16-gigabit predecessor [8], 2 gigabytes going to 3 [9].
Dies per wafer is the input a memory maker controls most directly. Processing a wafer costs what it costs, so 50 per cent more dies on it takes wafer cost per die to two thirds of the old number, a cut of about 33 per cent [11]. That holds only if yield per die does not fall and the extra patterning does not make the wafer dearer to run, and CXMT credits the node to "quadruple exposure" [4].
On the labels, 11.95nm sits 1.95nm above the 10nm process that the South China Morning Post attributes to Samsung and SK Hynix, roughly 20 per cent coarser [10][5].
A cost floor under commodity and mobile DRAM needs shipped bits at a price. CXMT's statement does not include yields, wafer starts or prices [12]. In my view the 2.25 figure is the one to test, because LPDDR5X parts get bought and opened, and a die measurement settles the density question without the company's help. The counter-case is narrower and duller: mass production here covers two 24-gigabit mobile parts [6], the older platform can carry most of the output, and a true density claim then changes nobody's cost floor this year.
The thesis fails if a teardown puts the 24-gigabit part's bit density well short of 2.25 times the 16-gigabit one, or if the 50 per cent counts dies printed and not dies sold. CXMT called the density gain a "quantum leap" [3].
What to watch
- Any CXMT or Chinese filing disclosure of G5 wafer starts or fab capacity, which is the number the density claim needs to matter commercially.
- Samsung or SK Hynix commentary on LPDDR5X pricing and mobile DRAM share in their next quarterly results.
- A handset maker naming a 24-gigabit CXMT part in a shipping phone.