The optical interconnect bill: $144B by 2030, and 63.7% of it is silicon photonics

A consultancy forecast attached to a Hong Kong IPO filing puts the data center optical interconnect market at $144.4 billion in 2030, up from $13.7 billion in 2024, a 48.1% compound annual growth rate ^[1]. That is a roughly 10.5-fold increase over six years in a layer that most buyers have historically treated as a line item under the accelerator, not alongside it ^[11].

Read the provenance before the number. The projection comes from a China Insights Consultancy report commissioned by Yuanjie Semiconductors, a Chinese laser-chip maker, as part of its listing documents, and draws on LightCounting data plus expert interviews ^[2]. Yuanjie makes the one component that both competing architectures require, because a laser chip is needed whether it feeds a co-packaged photonic integrated circuit or a pluggable module ^[8]. A forecast that grows the addressable market for lasers by an order of magnitude is, among other things, a sales document.

The engineering underneath it is less arguable. Copper is cheap, reliable and easy to integrate, but its power draw and signal loss rise sharply with bandwidth and distance ^[16]. Past a few hundred gigabits per lane, usable copper reach collapses to a meter or two before loss and power become unmanageable ^[6]. That is the constraint driving the transition, and it is a physical one, not a procurement fashion.

The share shift is the part worth planning around. Silicon photonics is projected to take 63.7% of 2030 revenue, up from 16.6% in 2020 ^[3], a swing of 47.1 percentage points in the mix ^[14]. At the headline market size that implies roughly $92 billion of silicon photonics revenue in 2030 ^[12]. The reason is manufacturing: silicon photonics patterns optical circuitry onto silicon using the same mature, high-volume CMOS processes as ordinary chips, which makes PICs mass-producible, while silicon cannot lase, so laser chips stay on more expensive III-V materials such as indium phosphide ^[9].

Co-packaged optics is what makes the mix shift matter for rack design. CPO pulls the optical engine out of the faceplate module and places the PIC directly on the switch or accelerator package, shortening the electrical path from inches of board trace to millimeters ^[7]. The laser cannot come along, because laser chips are heat-sensitive and the co-packaged part runs extremely hot, so it remains a separate device ^[8]. Pluggable transceivers stay the industry mainstay while link rates climb from 400G to 800G to 1.6T ^[10].

Money is already moving ahead of the forecast. Over the past year the AI industry has put more than $15 billion into co-packaged optics, photonic chips, faster transceiver modules and fiber, via new integration techniques, acquisitions of photonics startups and alliances among the largest players ^[4]. That single year of investment exceeds the entire 2024 market revenue of $13.7 billion ^[13], which tells you the spend is building capacity for a market that does not exist yet.

Watch the design-tool layer as the leading indicator. OpenLight and Tower Semiconductor have put OpenLight's photonic design kit inside Cadence's mainstream chip-design software, making laser-integrated 400G and 1.6T chips easier to design and bring to market ^[5], with an approach that integrates III-V laser material directly with silicon photonics ^[15]. Design kits landing in mainstream EDA flows precede design starts by a year or more, so that is where the 2030 mix gets decided. The other thing to watch is laser supply: it is the one part that cannot be CMOS-ified, and it sits on the critical path for both architectures ^[8][9].