Company
AI chip startup building data-center inference accelerators using in-memory computing, including its stacked-DRAM Raptor architecture.
d-Matrix's ISCA paper models up to 100 TB/s per card for Raptor, a stacked-DRAM inference accelerator. The figures come from modeling and the first cards are expected in Nvidia MGX racks in late 2027, so they have no bearing on inference hardware bought in the next year.
Reality
d-Matrix CTO Sudeep Bhoja says Raptor's 1,000 tokens per second per user comes from a simulated 72-card system, with full racks not due until Q4 2027. Whole-system speed, power and cost per request are still unmeasured, so buyers are working from early silicon tests and simulations.
Reality
Qualcomm's Tony Pialis told the AI Infra Summit in Santa Clara that tokens per watt is the new key metric in the AI war. The vendors in the room disagreed about which memory architecture gets them there.
Reality
Apple has not confirmed the plan and the M8 Ultra is years from release. Seven other companies have already licensed the same rack interconnect from Nvidia, and their dates are the ones a buyer can use.
Reality
The Dutch startup says craftwerk is designed to run AI agents, and the design details it has published so far are about ASICs and processor-memory co-design. Samsung, one of the biggest HBM suppliers, co-led the round.
Reality
The one measured number behind NVIDIA's tokens-per-megawatt pitch comes from Lambda's Blackwell cluster, where power reclaimed from static provisioning ran three extra nodes. Amazon's Annapurna Labs and d-Matrix got a line each.
Reality
In IEEE Spectrum's account of the 2026 compute market, reasoning and agentic workloads have pushed serving toward memory-heavy silicon, and Amazon now runs a single inference job across two vendors' chips.
Reality
d-Matrix says stacking compute on a co-designed DRAM die moves bits at roughly a sixth of HBM4's energy cost. It still has not said who fabricates the die.
Reality