Cadence's strategy director scopes its Level 5 chip-design agent claim to one domain

The three agents come from the companies that dominate chip design software ^[1]. They run the same loop. A reasoning model drives the flow ^[2]. It proposes a change, and an existing deterministic engine such as Xcelium, Jasper, Questa, Calibre or Fusion Compiler checks it, iteration after iteration until final verification ^[10]. The agent's job is to read intermediate results and choose the next action ^[10]. I think this is the correct design. Every decision still has to pass a proven engine, so the model never grades its own output ^[10].

The autonomy levels are graded on top of that loop, and no standard governs the grading ^[11]. Cadence's ladder runs from optimization AI through conversational LLM, complex reasoning and agentic workflows to full autonomy, defined as taking a design from spec to verification "with minimal human intervention" ^[12]. Synopsys climbs from single agents on one design step to multiple agents, then adaptive learning, then autonomous decisions ^[13]. It also says "human engineers will and must always be in the loop" ^[13]. Siemens does not number its levels, and so has nothing to qualify ^[11]. Tom's Hardware concluded that the ladders are marketing scaffolding over the same underlying architecture or loop ^[14]. In my view a level mostly says how long the loop runs before an engineer steps in.

Knoth's answer fits that view. Rob Knoth, Cadence's senior group director of strategy and new ventures, told Tom's Hardware Premium the demo was "what we call bounded Level 5 in one domain," with the bulk of the super-agent technology at "I'd say advanced Level 4" ^[4]. Cadence's June 1 Computex announcement said the agent had reached what the company calls Level 5 ^[3]. The reported interview does not say which domain the bound covers. Cadence deserves credit for scoping its own headline.

The domain matters because the claimed gains cluster in one place. They are largest in front-end design and verification, where RTL, testbenches and assertions are code and simulations return fast pass-or-fail answers ^[15]. Agents can run those simulations in parallel and take over triage, often the slowest part of the process ^[15]. Synopsys' March flow generates RTL from natural-language and formal specifications, writes unit-level testbenches, then enters a verification loop ^[16]. Its July claim put RTL validation gains at up to 50x ^[17].

For that multiple to hold on another team's design, several things would have to be true. The team would have to measure the same step the vendor measured. A similar share of its schedule would have to be lost waiting on human triage, since that wait is what the agent removes ^[15]. Its specifications would need to be clean enough to generate RTL from ^[16]. And the vendor's "up to" would have to describe a typical run, when the phrase marks the best one ^[8].

Empyrean's chairman, Liu Weiping, gave a layout figure on Sept. 9: four weeks cut to one, according to the South China Morning Post ^[7]. That is a 75% reduction in elapsed time ^[1]. It comes from one statement, reported secondhand, about a single task ^[7].