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IonQ decodes 408 logical qubits in real time on twelve cores of an Apple M4 Max
IonQ researchers report a real-time error-correction decoder that added under 0.3% to runtime at a CNOT error rate of 10^-4, and under 12% at five times that rate, on workloads simulated against the company's own proposed architecture.
The Investor · Invest desk
What happened
- Three IonQ researchers, Min Ye, Andrii Maksymov and Nicolas Delfosse, report the first real-time quantum error correction decoding pipeline running entirely on general-purpose hardware, a single 2024 Apple M4 Max CPU.
- The simulated workloads scaled to 408 logical qubits while executing over 1 million T gates and 1.3 million logical measurements, with the processing spread across 12 of the chip's 16 cores.
- At a physical CNOT error rate of 10^-4 the pipeline added less than 0.3% of computational stretch, and the stretch stayed below 12% at five times that error rate.
- No physical quantum computer ran at this scale; the workloads were simulated to match IonQ's proposed architecture, making the paper a proof of concept for the classical layer.
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Why it matters
- constraint Superconducting programmes keep the custom-accelerator line in their budgets: with syndrome cycles measured in microseconds rather than milliseconds, they need a decoder roughly a thousand times faster than the one IonQ ran on a laptop chip.
- decision With four of sixteen cores idle at a 0.3% penalty, IonQ can defer funding a decoder chip programme and put that engineering into qubit hardware instead.
- exposure The saving depends on measured error rates, because the penalty ceiling moves forty times for a five times worse CNOT error rate.
- cost The item taken off the build is custom FPGA or ASIC development, which Cryptobriefing calls expensive, slow and a source of supply-chain dependency, and which nobody involved has priced in public.
The two stretch figures do not scale with one another. Going from a physical CNOT error rate of 10^-4 to five times that rate moves the runtime penalty from under 0.3% to under 12% [5][6]. That is a forty-fold move in the penalty for a five-fold move in the errors [14].
Why a laptop chip can keep up at all is a question of timing. Trapped-ion syndrome extraction cycles run between 1 and 5 milliseconds [8], so even at the fast end the classical side gets roughly 1,000 microseconds to process each round of syndrome data [17]. Superconducting machines cycle in microseconds [13]. The pipeline was split into two streams, one absorbing the continuous syndrome flow and one resolving logical measurements on demand [7]. It ran on 12 of the M4 Max's 16 cores, leaving a quarter of the chip idle [4][15].
The workload was simulated, built to match IonQ's proposed architecture, with no physical quantum computer running at that scale [9]. Across 408 logical qubits, the 1.3 million logical measurements work out at about 3,190 each [16]. IonQ's Walking Cat blueprint, published in April 2026, sets out scaling past 10,000 physical qubits [10].
The cost claim rests on a comparison with custom silicon. Cryptobriefing reports that every earlier attempt at real-time decoding at meaningful scale needed specialized accelerators such as FPGAs or ASICs [11], and describes that custom silicon work as expensive, time-consuming and a source of extra supply-chain dependency [12]. The report does not attach a dollar figure to it [18]. If the pipeline holds on hardware, IonQ would not need to fund a decoder chip program with its own tape-outs and its own vendors.
In my view the schedule and dependency saving is the firmer part of this, and the capital saving is the part the material cannot size. A decoder accelerator may never have been a large line next to a trapped-ion system's optics and vacuum hardware. On that reading, what the paper shows is that decode at 408 logical qubits and over a million T gates is tractable at all [3].
Two outcomes would undercut it. Measured CNOT error rates on real hardware could land near 5x10^-4, putting the penalty at the 12% ceiling [6]. Or a decode load at Walking Cat's full physical scale [10] could stop fitting in the twelve cores this run used [4].
What to watch
- Measured CNOT error rates published from IonQ hardware, which decide whether the penalty sits at 0.3% or nearer the 12% ceiling.
- Whether a decode load at Walking Cat's 10,000-plus physical qubit scale still fits inside twelve general-purpose cores.
- Any superconducting group publishing a real-time decoder on general-purpose CPUs at comparable scale.