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Monaka's two SKUs are one core at two clocks, and the arithmetic says so
Fujitsu halved its vector width, moved the whole last-level cache onto a 5nm die, and dropped HBM. The published estimates scale exactly with base clock, which tells you what kind of number they are.
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What happened
- The design splits into three dies: a 2nm N2P core die, a 5nm SRAM die carrying the entire last-level cache, and a 5nm IO die.
- Two SKUs are planned: 350W air-cooled at 2.1 GHz base and 500W liquid-cooled at 2.9 GHz, samples now, volume production in 2027.
- HBM is gone in favour of 12-channel DDR5-8000, and the cores gain FP8 and INT8 matrix support for inference.
Why it matters
- constraint At 0.115 bytes per FLOP, the parts are provisioned for cache-resident and inference work, so HPC codes written around Fugaku's on-package bandwidth need re-tuning rather than recompiling.
- decision Buyers are not choosing between two designs but between two operating points on the same silicon, and the cheaper-to-cool one is marginally the better deal per watt.
- exposure The single number that decides whether a fully off-die last-level cache works in production is the one Fujitsu would not give when asked directly at the conference.
- precedent If holding leading-edge silicon under a third of package area yields well, cache and analog get exiled to trailing nodes as a default rather than an experiment.
Start with the estimates, because they are internally checkable. Divide 6,013 GFLOPS by 4,355 GFLOPS and you get 1.381. Divide 2.9 GHz by 2.1 GHz and you get 1.381 [19]. INT8 does the same thing: 96.2 over 69.7 is 1.380 [19]. These are not two measurements of two products. They are one core model evaluated at two points on a voltage-frequency curve [1][10], and the STREAM Triad figure, identical at roughly 500 GB/s on both parts, confirms the memory side was not modelled twice either [1].
That makes the per-watt comparison worth doing. The 350W part comes to about 12.4 GFLOPS per watt, the 500W part to about 12.0 [20]. The extra 150 watts of thermal budget buys 38 percent more throughput [20]. For a chip presented as engineered for power efficiency and subsidised by Japan's NEDO for green AI data centres [3], the air-cooled SKU is the one that carries the argument.
The vector narrowing looks less like a retreat once you back out the implied per-cycle work. At 144 cores and 2.1 GHz, 4,355 GFLOPS is 14.4 FP64 operations per core per cycle [21]. Two 256-bit SVE2 units doing fused multiply-add give 16 [15][21]. Fujitsu is claiming 90 percent of a narrow peak rather than a fraction of a wide one [21], and each vector unit is paired with its own 256-bit load/store path [15]. Chester Lam of Chips and Cheese asked why the datapath shrank from A64FX's 512-bit SVE, and Okazaki's answer was core size, cost and performance for the data centre [13]. The core measures about 1.47 mm2 [17].
Where it does cost something is bytes per FLOP. Twelve channels of DDR5-8000 peak at 768 GB/s, so 500 GB/s Triad is 65 percent of theoretical [22], and against DGEMM that works out to 0.115 bytes per FLOP on the 350W part and 0.083 on the 500W [23]. A64FX put HBM2 on package precisely for memory-bound HPC [14]. Monaka does not [15]. Codes tuned for Fugaku's bandwidth do not simply move across.
The packaging maths is the other place the strategy shows. One hundred and forty-four cores at 1.47 mm2 is 212 mm2 of core silicon alone, and Fujitsu holds 2nm to under 30 percent of total die area [9], which puts total package silicon somewhere north of 700 mm2 [24]. The 5nm tiers absorb everything that shrinks badly: the entire last-level cache [6], the IO die [7], and the low-dropout regulators, moved off 2nm because analog scales poorly there and placed directly under the floating-point units to drive per-core DVFS [11].
That is a real yield and schedule argument [9], and it is closer to Intel's Clearwater Forest base-tile approach than to AMD's V-Cache stacking [18]. It also has one unpaid bill. Ian Cutress asked what Fujitsu does to minimise core-to-core latency when core dies sit on opposite sides of the package and traffic routes through the IO die; the answer was face-to-face hybrid bonding, and no figures [12]. Everything else here is arithmetic you can audit. That one is not.
Note also what sits alongside the undervolting. Running about 30 percent below nominal voltage for roughly half the power [25] narrows electrical margins, and the core carries ECC or duplication on L1 and L2, parity on execution units and registers, and hardware instruction retry [16]. Those two design choices are hard to read as unrelated.
What to watch
- Whether Fujitsu publishes core-to-core or last-level cache latency figures before volume production in 2027.
- Whether the 350W air-cooled part holds its 2.1 GHz base under sustained all-core SVE2 load, given how much the undervolting scheme is carrying.
- A named baseline for the two-times AI performance and 50% TCO claims, or third-party results from the evaluation samples.
Clarity's read
What the record supports and how the coverage leans. The claims behind it follow.
Reality
- Evidence62
- Adoption22
- Hype gap+32
- Incentives70
- Confidence55
Claim ledger
Ranked by verification strength, evidence, and original report placement.
- [1]
Fujitsu estimates the 350W SKU at 4,355 GFLOPS in DGEMM and 69.7 TOPS in INT8, and the 500W SKU at 6,013 GFLOPS and 96.2 TOPS, with both parts rated around 500 GB/s in STREAM Triad.
- [2]
Okazaki described the voltage technique as delivering energy saving comparable to moving one generation beyond the 2 nanometers, achieved with custom SRAM and a proprietary CAD flow tuned for non-standard low-voltage operation.
- [3]
Okazaki, lead architect of Fujitsu's processor development team, presented Monaka as a made-in-Japan CPU specifically engineered for AI performance and power efficiency, built for what Fujitsu calls green AI data centers and subsidised by Japan's New Energy and Industrial Technology Development Organization.
- [4]
Fujitsu presented a detailed look at its 144-core Monaka server CPU at Hot Chips 2026 on August 24.
- [5]
Monaka runs dual 256-bit SVE2 vector units, down from the 512-bit SVE in its A64FX predecessor.
- [6]
Monaka's entire last-level cache sits on a separate 5nm die beneath the 2nm compute die.
- [7]
Monaka splits into three dies: a 2nm core die on TSMC N2P, a 5nm SRAM die on TSMC N5 holding the whole last-level cache, and a 5nm IO die.
- [8]
The core die stacks face-to-face on top of the SRAM die through hybrid bonding, sitting on the cooling side because it runs hottest, while the IO die connects to the SRAM die across a silicon interposer.
- [9]
Fujitsu keeps 2nm silicon under 30% of total die area; Okazaki said the split lets Fujitsu accelerate time to market for its 2nm chip by pushing everything that shrinks poorly onto the 5nm SRAM and IO dies.
- [10]
Monaka ships in two SKUs: a 350W air-cooled part at 2.1 GHz base and a 500W liquid-cooled part at 2.9 GHz base, with evaluation samples available now and volume production in 2027.
- [11]
Fujitsu moved the low-dropout voltage regulators onto the 5nm SRAM die because analog circuits scale poorly at 2nm, and placed them directly beneath the core's floating-point units to feed per-core dynamic voltage and frequency scaling.
- [12]
Dr. Ian Cutress of More Than Moore asked whether Fujitsu was doing anything special to minimise core-to-core latency given that core dies sit on opposite sides of the package with traffic routing through the IO die; Fujitsu pointed to the face-to-face hybrid bonding and declined to disclose latency figures.
- [13]
Asked by Chester Lam of Chips and Cheese why the vector datapath narrowed from 512-bit SVE to 256-bit SVE2, Okazaki said the chip is built for the data centre and that Fujitsu wanted to minimise core size for the best cost and performance, with the narrower units also cutting SIMD width for general-purpose code.
- [14]
A64FX, the 7nm CPU that powered Fugaku and was the first chip to implement Arm SVE, paired its 512-bit vectors with on-package HBM2 for memory-bound HPC.
- [15]
Monaka drops HBM for 12-channel DDR5 at 8000 MT/s and runs two 256-bit SVE2 units per core, each aligned to a 256-bit load/store unit, with FP8 and INT8 matrix support added for inference.
- [16]
The core carries mainframe-class reliability features: ECC or duplication on L1 and L2 caches, parity checks on execution units and registers, and a hardware instruction-retry mechanism to recover from transient errors.
- [17]
Monaka runs a three-level TAGE branch predictor and six ALUs, on a core Fujitsu measures at roughly 1.47 mm2.
- [18]
Putting the full last-level cache on a distinct stacked die separates Monaka from AMD's 3D V-Cache, which bonds extra SRAM on top of a compute die that already carries its own L3, and lines it up closer to Intel's Clearwater Forest, where local cache sits in a base tile with compute stacked above.
- [19]
The 500W SKU's estimated throughput exceeds the 350W SKU's by exactly its base-clock ratio: 6,013/4,355 = 1.381 and 2.9/2.1 = 1.381, with INT8 at 96.2/69.7 = 1.380, so both estimates are the same per-clock model scaled by frequency.
- [20]
Per watt the 350W part delivers about 12.4 GFLOPS/W (4,355/350) against about 12.0 GFLOPS/W for the 500W part (6,013/500), and the extra 150W buys 38% more DGEMM throughput.
- [21]
The 350W estimate implies 14.4 FP64 operations per core per cycle (4,355 / (144 x 2.1)), against a theoretical 16 for two 256-bit SVE2 fused multiply-add units, or 90% of peak; the 500W estimate gives the same 90%.
- [22]
Twelve channels of DDR5-8000 give a theoretical peak of 768 GB/s (12 x 8 GT/s x 8 bytes), so the roughly 500 GB/s STREAM Triad rating is about 65% of peak.
- [23]
Against DGEMM throughput the memory rating works out to 0.115 bytes per FLOP on the 350W part (500/4,355) and 0.083 on the 500W part (500/6,013).
- [24]
At 1.47 mm2 per core, 144 cores account for about 212 mm2 of silicon; if that 2nm tier is held under 30% of total die area, total package silicon exceeds roughly 700 mm2.
- [25]
Fujitsu claims up to two-times AI performance and over 50% TCO reduction against unnamed comparisons, and credits ultra-low-voltage operation, running the core around 30% below nominal voltage for roughly half the power, for holding 144 cores inside the 350W envelope.
Sources
1 independent publisher whose own reporting we read for this story.
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