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Fujitsu halved its vector width, moved the whole last-level cache onto a 5nm die, and dropped HBM. The published estimates scale exactly with base clock, which tells you what kind of number they are.
The Engineer · Build desk
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Start with the estimates, because they are internally checkable. Divide 6,013 GFLOPS by 4,355 GFLOPS and you get 1.381. Divide 2.9 GHz by 2.1 GHz and you get 1.381 [1]. INT8 does the same thing: 96.2 over 69.7 is 1.380 [1]. These are not two measurements of two products. They are one core model evaluated at two points on a voltage-frequency curve [15][7], and the STREAM Triad figure, identical at roughly 500 GB/s on both parts, confirms the memory side was not modelled twice either [15].
That makes the per-watt comparison worth doing. The 350W part comes to about 12.4 GFLOPS per watt, the 500W part to about 12.0 [2]. The extra 150 watts of thermal budget buys 38 percent more throughput [2]. For a chip presented as engineered for power efficiency and subsidised by Japan's NEDO for green AI data centres [19], the air-cooled SKU is the one that carries the argument.
The vector narrowing looks less like a retreat once you back out the implied per-cycle work. At 144 cores and 2.1 GHz, 4,355 GFLOPS is 14.4 FP64 operations per core per cycle [3]. Two 256-bit SVE2 units doing fused multiply-add give 16 [12][3]. Fujitsu is claiming 90 percent of a narrow peak rather than a fraction of a wide one [3], and each vector unit is paired with its own 256-bit load/store path [12]. Chester Lam of Chips and Cheese asked why the datapath shrank from A64FX's 512-bit SVE, and Okazaki's answer was core size, cost and performance for the data centre [10]. The core measures about 1.47 mm2 [14].
Where it does cost something is bytes per FLOP. Twelve channels of DDR5-8000 peak at 768 GB/s, so 500 GB/s Triad is 65 percent of theoretical [4], and against DGEMM that works out to 0.115 bytes per FLOP on the 350W part and 0.083 on the 500W [5]. A64FX put HBM2 on package precisely for memory-bound HPC [11]. Monaka does not [12]. Codes tuned for Fugaku's bandwidth do not simply move across.
The packaging maths is the other place the strategy shows. One hundred and forty-four cores at 1.47 mm2 is 212 mm2 of core silicon alone, and Fujitsu holds 2nm to under 30 percent of total die area [6], which puts total package silicon somewhere north of 700 mm2 [6]. The 5nm tiers absorb everything that shrinks badly: the entire last-level cache [3], the IO die [4], and the low-dropout regulators, moved off 2nm because analog scales poorly there and placed directly under the floating-point units to drive per-core DVFS [8].
That is a real yield and schedule argument [6], and it is closer to Intel's Clearwater Forest base-tile approach than to AMD's V-Cache stacking [18]. It also has one unpaid bill. Ian Cutress asked what Fujitsu does to minimise core-to-core latency when core dies sit on opposite sides of the package and traffic routes through the IO die; the answer was face-to-face hybrid bonding, and no figures [9]. Everything else here is arithmetic you can audit. That one is not.
Note also what sits alongside the undervolting. Running about 30 percent below nominal voltage for roughly half the power [16] narrows electrical margins, and the core carries ECC or duplication on L1 and L2, parity on execution units and registers, and hardware instruction retry [13]. Those two design choices are hard to read as unrelated.
Ranked by verification strength, evidence, and original report placement.
Fujitsu estimates the 350W SKU at 4,355 GFLOPS in DGEMM and 69.7 TOPS in INT8, and the 500W SKU at 6,013 GFLOPS and 96.2 TOPS, with both parts rated around 500 GB/s in STREAM Triad.
Okazaki described the voltage technique as delivering energy saving comparable to moving one generation beyond the 2 nanometers, achieved with custom SRAM and a proprietary CAD flow tuned for non-standard low-voltage operation.
Okazaki, lead architect of Fujitsu's processor development team, presented Monaka as a made-in-Japan CPU specifically engineered for AI performance and power efficiency, built for what Fujitsu calls green AI data centers and subsidised by Japan's New Energy and Industrial Technology Development Organization.
Fujitsu presented a detailed look at its 144-core Monaka server CPU at Hot Chips 2026 on August 24.
Monaka runs dual 256-bit SVE2 vector units, down from the 512-bit SVE in its A64FX predecessor.
Monaka's entire last-level cache sits on a separate 5nm die beneath the 2nm compute die.
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Evidence-backed comparisons of source perspectives and observed adoption signals. Read the methodology
Which Builder, Operator, and Investor concerns the observed source mix emphasized—not a truth score.
Evidence, demonstrated adoption, hype gap, incentives, and confidence are assessed independently, each on its own current evidence. How these are measured.
Rich first-party disclosure, zero independent measurement
The design record is unusually specific and directly attributable: die split and process nodes, hybrid-bonding topology, LDO relocation, RAS features, predictor and ALU counts, core area, and on-record architect answers to two named analysts. That supports the architectural claims strongly. Every performance number, however, is a Fujitsu estimate for a pre-production part, the headline AI and TCO multipliers have no named baseline, and core-to-core latency was withheld. The internal arithmetic is checkable and self-consistent, which raises confidence in what the numbers are without validating what they mean.
Evaluation samples only; volume a year out
Adoption is pre-commercial. Samples exist and volume production is stated for 2027, but the sources name no customer, OEM platform, cloud deployment, price or shipped unit. The only named forward commitment is to the successor Monaka-X inside FugakuNEXT, which is a design intention for a different, 1.4nm-class part rather than Monaka deployment. That is enough to register real productisation momentum and no more.
Vendor framing runs ahead of the measurements
The claims that travel furthest are the softest: up to two-times AI performance and over 50% TCO reduction against comparisons Fujitsu does not name, and an energy saving characterised as equivalent to a node beyond 2nm. Meanwhile the two SKUs' throughput figures are one per-clock model scaled by frequency rather than two independent results, the STREAM rating sits at about 65% of DDR5 peak, and latency data is withheld. The architectural disclosure itself is not overstated — the packaging and cache-die design are genuinely distinctive — so the gap is confined to the performance and efficiency narrative.
Subsidised national program, vendor-controlled numbers
Every substantive number originates with the chip's vendor at its own conference session, and the program is publicly subsidised by NEDO under a green data center target, with a made-in-Japan sovereignty framing that the same report notes is complicated by TSMC manufacturing. Fujitsu therefore has both commercial and political reasons to present favourable efficiency and TCO framing. The publisher also ran the coverage as a temporarily free premium article tied to Hot Chips week, a traffic-side incentive worth naming, though it does not bear on the technical content.
Single publisher, but internally checkable
Only one outlet covered this cluster, so there is no corroboration or contradiction from a second reporter and no way to cross-check transcription of the presented slides. Offsetting that, the report carries direct quotes, names the analysts who asked questions, and supplies enough figures that the derived arithmetic verifies internally to three decimal places. Confidence in the architectural facts is fairly high; confidence in performance, TCO and adoption trajectory is materially lower.
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