Arm's AGI CPU finally has a spec sheet, and its best number needs DIMMs nobody sells yet

On-die memory controllers are a latency purchase, and Arm paid for them in silicon. Each of the two AGI chiplets carries compute and I/O on the same N3P die ^[5], wired with an 8x9 CMN-S3 mesh, snoop filtering and a Super Home Node that distributes traffic through the chip ^[7], inside a coherency domain Arm built to reach past the die and the socket ^[8]. Memory traffic never crosses to a separate I/O die, which is how Arm arrives at a sub-100 ns DRAM latency claim ^[1]. Tom's Hardware reads the same floorplan as a trade: locality and bandwidth bought at the expense of the compute density, modularity and manufacturing ease that AMD gets from hanging compute chiplets off a central I/O die ^[11][13].

The numbers that matter to a purchase order are per core. Twelve DDR5 channels per socket, six on each chiplet ^[16], at DDR5-8800 gives 844.8 GB/s, and the arithmetic closes exactly at 12 x 8 bytes x 8800 MT/s ^[15][1]. Spread across 136 exposed cores that is 6.2 GB/s per core ^[18]. On the 64-core part, assuming it keeps both chiplets' controllers, the same bus serves 13.2 GB/s per core ^[19]. Against a 300 W socket ^[9], 136 cores works out to 2.2 W each ^[17].

That peak only exists if the DIMMs do. Tom's Hardware notes DDR5-8800 has still to reach the market ^[1], so anything quoted against an x86 bid this cycle carries a memory-speed contingency Arm does not control, and the fallback figure scales down with whatever grade is orderable in volume.

The cache disclosure does not reconcile. Arm's product-level number is up to 272 MB of system-level cache ^[6], but the per-chiplet detail is 128 MB of distributed SLC ^[7], which sums to 256 MB ^[24]. Meanwhile 272 is exactly 136 cores times 2 MB of L2 ^[23]. Either the top-line figure is aggregate L2 wearing a different label, or there is 16 MB of last-level cache Arm has not broken out. Cache per core is not a rounding error in a bid model.

Two 70-core chiplets is 140 physical cores and 100 billion transistors per socket ^[20][21] against a 136-core ceiling, so four cores of harvest slack ^[10]. The 64-core configuration exposes 46% of the physical cores ^[22], a wide bin for a part that still has to drive 96 lanes of PCIe 6.0 with CXL 3.0 on top ^[9].

Arm's original introduction gave key specifications and said nothing at all about performance ^[14]. Hot Chips added the architecture, the shipping configurations and a statement that the silicon works as planned ^[2]. That is enough to build a bandwidth and power model against, and not enough to build a throughput comparison, which is the first thing the x86 incumbents will put in front of a buyer.