The compounding is where a budget breaks, not the single quarter. Take Counterpoint's 80% to 90% for the first quarter of 2026 [3] and multiply it by the 13% to 18% TrendForce expects in the third [8], and a module indexed at 100 going into the year leaves the third quarter somewhere between 203 and 224, with nobody in this material quoting a figure for the quarter in between [1]. Marvell's own read on the same market is steeper, 90% to 95% in a single quarter [4], and it is Marvell that expects memory to absorb roughly 30% of hyperscaler spend in 2026 against about 8% in 2023 and 2024 [5], which is 3.75 times the share and 22 points of budget that have to come out of whatever else was on the invoice [2].
Which is what makes the recycling a capital decision rather than a housekeeping one. Google's confirmation reaches us second hand, via Cryptopolitan quoting supply chain director Nikhil Cherian, that DDR4 is being pulled from retired servers into new AI machines because supply is extremely tight [1], and Cherian adds that the pivot has not solved the problem and that the only durable fix is memory makers building capacity fast [2]. Read that as an internal transfer price: the retired rack stops being scrap with a residual value and becomes bonded inventory of memory bandwidth, so the decommissioning calendar now answers to procurement. Meta's published numbers size the trade at as much as 25% off server count on some inference workloads across millions of machines [6], three boxes doing the work of four [4], with average latency on distributed caches down about 29% [7].
The workaround is neither free nor general. Meta found that off-the-shelf CXL parts bundle the controller with the DRAM, which locks out the DDR4 stockpile you were trying to reuse [12], and that expansion memory behind those stacks ran roughly ten times slower on bandwidth and about 60% worse on latency than directly attached DRAM [13], which is why it built the Vistara ASIC and wrote software that switches the tier off when delay becomes unacceptable [14]. That is two hyperscaler engineering programmes pointed at memory pooling, which is headcount and mask cost not pointed at anything else. Marvell's Khurram Malik describes the same behaviour from the supplier side, hyperscalers extending DDR4 life with CXL controllers rather than letting modules go obsolete on DDR5-only platforms [15].
This is probably wrong, but the 2029 date is carrying more weight than the evidence puts on it. The specific claims are that SK Hynix's Y2 plant will not reach cleanroom until mid-2029 despite about $38 billion committed to two fabs [9], and that ChangXin is stuck near 240,000 wafers a month under US export controls at yields Counterpoint puts 42% below Samsung and SK Hynix, call it 139,200 peer-equivalent wafers [10][11][3]. Neither claim says anything about what the three firms holding roughly 94% of the market [17] choose to run through the fabs they already own. And if you compounded TrendForce's low end across the thirteen quarters between the first quarter of 2026 and that cleanroom date you would arrive at 4.9 times the price [5], which no buyer pays, so something gives long before the silicon lands. Kwak Noh-Jung's view that the market stays short to the end of 2030 [16] comes from a man with inventory to sell.
The falsifier is clean enough: if the first-quarter spike was allocation panic and double-ordering rather than physical scarcity, renewals stop clearing at those levels and the recycling programmes turn out to have been an expensive hedge against a price that had already topped. The line worth funding is the 30% of spend; the line worth doubting is the 2029.
