ASML's 40 percent throughput gain lands five years after Samsung's High-NA line starts

Twelve inches against six is twice the linear dimension and four times the mask area ^[19]. The throughput gain ASML technology chief Marco Pieters attaches to that change is 40 percent ^[7]. The two figures measure different things: throughput is wafers per hour, and a larger stencil only pays off if the die being printed is large enough to use the enlarged field ^[13].

The bigger effect is on chip design itself, not on a throughput number. The six-inch limit capped how large a single chip could be, which pushed manufacturers into stacking chips vertically and connecting them in complex ways, and that drove up cost and complexity ^[11]. Lifting the cap removes a reason to disaggregate a design in the first place. For anyone currently paying for advanced packaging to route around the reticle limit, that is worth more than 40 percent.

It also arrives well after the tools. On the reported dates, Samsung books five years of High-NA production at the six-inch field size and TSMC three ^[20][21]. At up to $400 million a unit ^[3], the first fleets are depreciated against exactly the geometry the mask change is meant to fix, and anything taped out for those lines in the interim lives inside the old limit.

The 40 percent is a vendor figure, and the switch to twelve inches has long been considered complicated and expensive ^[24]. Two things have to hold for the number to transfer to a given fab: the products running on those tools need dies large enough to consume the extra field, and the twelve-inch mask supply chain has to work at production quality, which is what the 2031 test line exists to establish ^[8]. TSMC's stated objection was cost: it argued the productivity gains did not justify the higher costs, and the reversal is reported without a new cost figure ^[9]. TSMC's side of that cost equation still has not been made public.

None of the Chinese effort touches this window. China's push, as the Financial Times reported and the-decoder relayed, targets DUV at 193 nanometers rather than EUV at 13.5 ^[14], with multi-patterning to reach finer structures at greater effort and cost than EUV ^[15]. Yuliangsheng aims to build twelve DUV machines by the end of the year and remains far behind ASML ^[16]. Bernstein analyst Lin Qingyuan said a DUV prototype alone is not enough, and that the job needs thousands of suppliers and customers plus a central orchestrating force ^[17]. The optics make the point: Yuliangsheng uses Zeiss lenses, Zeiss says it sells its optics only to ASML, and the FT's sources point at the secondary market, which is one way to describe a supply chain ^[18]. Huawei, for its part, is investing across the lithography chain and brokering deals with fabs including SMIC ^[22].

So the decision in front of a design team is narrower than the 2028 and 2030 commitments suggest. It is whether to plan one more product generation around a six-inch reticle, because on ASML's own schedule the tool ships up to five years before the mask that makes it faster ^[20].