Harry Juhyun Kim

XCENA demonstrates a 2TB CXL card that runs the work where the bytes already sit

MX1 puts 3,072 in-order RISC-V cores and up to 2TB of DDR5 behind a CXL 3.2 link, betting that bandwidth-bound inference work is cheaper to run on the card than to drag across 128GB per second of host interface.