Astrus raises $12 million to train a chip-layout model on data it generates itself

Moon's case rests on one sentence about volume. "In the next year, we'll have more physical design data than the rest of the world combined," he said ^[12].

The reason he needs to say that is scarcity. There is a large amount of public logic design data available to train a language model on, and, Moon said, none for physical design ^[8]. "The physical design side is incredibly secretive. There is no public data. This is because companies like Apple or TSMC, there's no way they're going to let their physical design data out," he said ^[9]. So Astrus makes its own: after partnering with what Moon called "the largest bleeding-edge foundries in the world" to understand their manufacturing requirements, its developers applied reinforcement learning to produce what he called "infinite synthetic data" ^[10]. "We essentially have this AI learn. It plays around in this physics environment that understands the manufacturing rules, and it generates synthetic data. And you can just keep training this thing, and it'll get better and better," he said ^[11].

If the generator is unbounded, beating the rest of the world on sample count is a function of how long the trainer runs. What decides the product is whether the environment's manufacturing rules match a real foundry's rules on a real part, and Moon described those partners only as the largest bleeding-edge foundries in the world without naming them ^[22].

The round is $12 million USD and $16 million CAD ^[1], an implied 0.75 US dollars per Canadian dollar ^[19]. Astrus had previously announced $11 million CAD for the same problem ^[14], so disclosed equity across the two rounds is $27 million CAD, about $20 million USD ^[20]. That pays for an October launch and a bigger team ^[13]. Moon also cited a global integrated circuit market worth more than $800 billion USD this year ^[5]; the round is 0.0015 percent of it ^[21]. The $800 billion counts chips sold, and Astrus would be paid out of design budgets.

Moon said potential customers include major semiconductor manufacturers, and that Astrus is looking at collaborations with companies working on logic design tools ^[16]. He said Astrus can still partner with the LLM providers, which handle the intent side, but that once a customer has a design it wants to turn into manufacturing reality, the physical design side has to be dealt with ^[17]. The two firms he named as the least likely to release layout data, Apple and TSMC, sit on the customer side of that list ^[9].

Either the environment is accurate, analog layout time compresses, and the proprietary corpora held by chipmakers stop being a defence. Or the synthetic layouts satisfy simulation but not the fab, and the tool becomes a first-pass assistant with the applied physicists Moon described still doing the final work ^[4]. Or manufacturers decline to hand performance-critical blocks to an outside model at all, and Astrus reaches them only through the logic-tool vendors it wants to partner with ^[17]. The October date is the first checkable commitment in the record.

Moon said Astrus is not following other Canadian semiconductor companies to the United States. "We'll probably have a go-to-market team in the US, but Canada is really well-positioned," he said, citing Rich Sutton at the University of Alberta and Geoff Hinton at Toronto ^[15]. He expects the product "to take off like wildfire because this is one of the biggest bottlenecks in chip design process" ^[18].