India's eight-year 3nm target starts at a 180nm line in Mohali

According to India Today, Vaishnaw said the country "now has 40nm technology" ^[3]. The dev.to writeup takes that to mean design capability and process know-how acquired through partnerships and R&D, and states that no Indian fab commercially ships 40nm today ^[4]. The only operational fab, the government-owned Semi-Conductor Laboratory in Mohali, runs an 8-inch line at roughly 180nm and supplies strategic and space-grade parts ^[5]. The same source puts that line about fifteen technology generations behind the leading edge ^[6]. The India Semiconductor Mission's own 28nm to 110nm range is prospective for the new fabs; SCL ships none of it ^[7].

The statement was published in late August 2026 ^[1], so eight years runs to 2034 ^[18]. Semicon 2.0 lists the first new fab commissioning for 2028 ^[8]. That leaves six years between a mature-node fab starting up and a 7nm-to-3nm technology claim coming due ^[19]. The fab in question, Tata Electronics with Taiwan's PSMC at Dholera, is built around mature process nodes and is still under construction at roughly Rs 91,000 crore ^[9].

One mature-node fab at Rs 91,000 crore is about 71 percent of the entire Rs 1,27,500 crore Semicon 2.0 outlay ^[20], and that outlay covers design, equipment, materials, packaging, R&D and talent across six pillars ^[2]. The source prices a single advanced fab in the tens of billions of dollars and the whole Semicon 2.0 budget at about $15 billion ^[10][11]. For the eight-year line to mean wafers, that budget would also have to seed EUV lithography tools, ultra-pure chemicals and gases, and specialty materials, which the source says all still need domestic suppliers ^[12].

What exists now is the design layer. Under the Design Linked Incentive scheme, 23 chip-design projects have been sanctioned with Rs 803.08 crore in project outlay including EDA tools, per a July 2025 PIB release ^[13], which works out to about Rs 35 crore per project ^[21]. The same release counts 72 startups and 278 academic institutions given access to commercial EDA software ^[14]. Semicon 2.0 materials put about 70,000 students trained on chip-design tools across 332 universities ^[15].

The dev.to piece argues India is sequencing this in the right order: mature-node volume at Dholera, then advanced packaging, then 28nm-class production, then faster node progress with partners ^[16]. It also argues that manufacturing experience compounds slowly and that a production team's accumulated yield knowledge cannot be bought the way design know-how can ^[17]. Japanese process and materials partnerships are named as one realistic path to climb nodes faster ^[22]. On this record, the eight-year number is a technology target. What a buyer can plan around before 2030 is design work, packaging and hiring.