Build 1 publisher2 min readPublished September 18, 2026 at 12:45 AM PDT

Walking the stall counter down puts SM120's fixed-latency window at four cycles

A dev.to microbenchmark hand-encodes SASS control words on SM120 and shrinks each stall until the consumer reads stale data; interleaving independent pairs then spreads the same four cycles across more producers.

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Illustration accompanying Walking the stall counter down puts SM120's fixed-latency window at four cycles

What happened

A dev.to post microbenchmarks SM120 by hand-encoding the Stall field of each producer and walking it down until the consumer reads a stale register, following Jia et al.'s Volta method.
Huerta et al. found the required producer stall does not change with register bank conflicts, which they take as ruling out a variable-latency Operand Collector stage during instruction execution.
The FADD-to-FFMA pair runs in five cycles, and interleaving two, three and four independent pairs takes six, seven and eight cycles, one extra cycle per pair added.
The post reports that a Stall Counter of 4 does not satisfy every data dependency, naming producer and consumer instruction type, forwarding and write-back paths, execution pipeline and ILP among the factors.
Every measurement ran on SASS-Testbench, with registers R52 to R60 zeroed ahead of each snippet so uninitialized values could not mask a bad read.

Compiled by The EngineerSomething wrong?How this is made

Why it matters

constraint Anyone emitting SASS by hand cannot rely on one global latency constant; the stall value has to be chosen per producer-consumer pair, per pipeline, and against whatever independent work sits between them.
exposure An under-encoded stall hands the consumer a stale register without faulting or stalling, so the defect surfaces as bad numerics well downstream of the instruction that caused it.
capability Because the wait can be spread across independent producers, the published snippets take issue rate from 0.4 instructions per cycle at one pair to 1.0 at four, a factor of 2.5 for the same dependency structure.
contradiction The post's stated finding is that a stall of 4 is not always sufficient, yet every threshold in the published excerpt, arithmetic pairs and MOV pairs alike, is consistent with 4.

In Huerta et al.'s model the compiler owns the dependency and the hardware only runs the wait it was handed ^[1]. For a fixed-latency producer that wait is the Stall field of the control word; variable-latency producers get a Dependence counter instead ^[2]. Take a cycle off the Stall field and no interlock catches it. The stopping condition in the Jia-style method is that the consumer's result becomes incorrect, and the last stall value that still yields a correct result is recorded as the producer's latency ^[3].

The ILP snippets show where the wait goes. At two pairs the producers carry S01 and S03, at three they carry S01, S01 and S02, and at four every instruction in the block carries S01 ^[9]^[10]^[11]. The stalls ahead of the first FFMA sum to 4 in all three cases: 1+3, 1+1+2, and 1+1+1+1 ^[15]. The independent producers sitting between the first FADD and the first FFMA absorb the wait.

Those cycle counts are a claim about a hand-built snippet. Every producer in the series is a FADD reading the same two source registers, R8 and R9, every consumer is an FFMA multiplying by RZ, and nothing in the series touches memory ^[20]. For the numbers to mean anything in code you did not hand-encode, the compiler would have to pick the same stall values for the same instruction pairs, and your producers would have to issue down the same pipeline.

Two of the results the post rests on are cited to Huerta et al. rather than re-measured: the bank-conflict sweep behind the Operand Collector conclusion, and the finding that MOV-MOV and MOV-LDG latencies differ. They attribute that difference to a possible forwarding path inside the pipeline MOV belongs to ^[4]^[5]. What this post adds is the comparison across classes of fixed-latency instruction and the ILP series ^[19]. In its own MOV-MOV measurement the producer carries S04 and the block runs in 5 cycles, the same shape as FADD-FFMA ^[13]^[8]. The published text does not include the minimum stall figures in the sentences that report them, so the only readable values are the encoded S-fields in the listings. The MOV series breaks off partway through the ILP=2 case ^[14].

What to watch

Published stall thresholds for the cross-class pairs the post says it investigates, which is where a counterexample to 4 would have to appear.
A corrected version of the post that prints the minimum stall figures alongside the listings.
A reproduction of the ILP series on a second SM120 part or a different NVIDIA architecture.

Claim ledger

Ranked by verification strength, evidence, and original report placement.

[8]
The single-pair snippet is FADD R12, R8, R9 with control field S04 followed by FFMA R52, RZ, RZ, R12 with S01, and the snippet runs in 5 cycles.
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[9]
At ILP = 2 the snippet is FADD R12, R8, R9 at S01, FADD R14, R8, R9 at S03, then FFMA R52, RZ, RZ, R12 at S01 and FFMA R54, RZ, RZ, R14 at S01, and it runs in 6 cycles.
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[10]
At ILP = 3 the three FADD producers carry S01, S01 and S02, the three FFMA consumers each carry S01, and the snippet runs in 7 cycles.
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[11]
At ILP = 4 the four FADD producers each carry S01, the four FFMA consumers each carry S01, and the snippet runs in 8 cycles.
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[12]
The post states that when both the producer and the consumer are arithmetic instructions, the "latency is 4" model proposed by the community and the literature is consistent with the observations.
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[1]
Huerta et al., in "Dissecting and Modeling the Architecture of Modern GPU Cores", propose that modern NVIDIA GPUs express dependency constraints through compiler-encoded control fields, and that the hardware merely performs the corresponding wait and counting mechanisms according to those encodings.
ReportedSupportedView cited source
[2]
Data dependencies of fixed-latency instructions are managed by the Stall counter field, while those of variable-latency instructions are managed by the Dependence counter.
ReportedSupportedView cited source
[3]
The methodology follows Jia et al.'s "Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking": construct a producer A and a consumer B that depends on its result, progressively decrease the stall in the control word for a fixed-latency A until the result used by B becomes incorrect, and take the last stall value that still produces a correct result as the latency of A.
ReportedSupportedView cited source
[4]
Huerta et al. measured the producer Stall Counter values that satisfy producer-consumer data dependencies under different register bank conflict conditions, and found that this value does not vary with bank conflicts, which rules out the existence of a variable-latency Operand Collector stage during instruction execution.
ReportedSupportedView cited source
[5]
Huerta et al. measured the latency at which the first MOV's result can be correctly obtained by the second instruction in MOV-MOV and MOV-LDG instruction pairs, found that the two latencies differ, and point to the possible existence of a data forwarding path inside the pipeline to which MOV belongs among the fixed-latency instructions.
ReportedSupportedView cited source
[6]
The post finds that simply setting the Stall Counter to 4 does not satisfy data dependencies in all cases, and lists producer generation timing, data forwarding or write-back paths, consumer source-operand read timing, producer instruction type, consumer instruction type, execution pipeline, and instruction-level parallelism among the factors involved.
ReportedSupportedView cited source
[7]
All measurements in the post were performed using SASS-Testbench, and prior to the microbenchmark snippet R52-R60 were zeroed to eliminate interference from uninitialized values.
ReportedSupportedView cited source
[13]
The MOV-MOV snippet is MOV R12, R8 at S04 followed by MOV R52, R12 at S01, and it runs in 5 cycles.
ReportedSupportedView cited source
[14]
In the published text of the post, the sentences reporting the minimum stall value that ensures a correct read do not contain a figure, and the text breaks off partway through the MOV ILP = 2 case.
ReportedSupportedView cited source
[18]
The post, headlined "Exploring Result Visibility of Fixed-Latency Instructions on the SM120 Architecture", was published on dev.to.
ReportedSupportedView cited source
[19]
The post further investigates the producer Stall Counter conditions that satisfy producer-consumer data dependencies between different classes of fixed-latency instructions, and introduces ILP.
ReportedSupportedView cited source
[15]
In each ILP case the stall values encoded on the producers ahead of the first FFMA add up to 4.
DerivedSupported1 source— sign in to open
[16]
Block time rises by exactly one cycle for each producer-consumer pair added, from 5 cycles at one pair to 8 cycles at four, so total cycles equals 4 plus the number of pairs.
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[17]
Issue rate over the measured block goes from 0.4 instructions per cycle at one pair to 1.0 at four pairs, a factor of 2.5.
DerivedSupported1 source— sign in to open
[20]
In the ILP series every producer is a FADD reading source registers R8 and R9, every consumer is an FFMA of the form FFMA Rm, RZ, RZ, Rn, and no instruction in the series references memory.
DerivedSupported1 source— sign in to open

Sources

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dev.to
1 article · September 18, 2026
Exploring Result Visibility of Fixed-Latency Instructions on the SM120 Architecture

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Clarity analysis

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Perspective Coverage

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This is aimed squarely at whoever writes the control words. The listings are complete: a lone FADD at S04 into an FFMA at S01, then the S01/S03 pair, then S01/S01/S02, then four S01s, each with its block time of 5, 6, 7 and 8 cycles. The post does not print the number its own method produces; each sentence reporting the minimum stall for a correct read stops before the figure. A builder can still recover 4 by adding the producer stalls in each snippet, and the author says the community's "latency is 4" model matches for arithmetic pairs and again for MOV pairs. The same author warns that a flat 4 is not always enough, and names forwarding paths, consumer operand-read timing and pipeline among the reasons.

Reality

Evidence, adoption, hype gap, incentives and confidence, each read independently from the current record on the scale shown beneath it. How these are measured.

Evidence45

0100

Checkable method, missing numbers

Every snippet is printed with its control fields and block time, and the technique is credited to Jia et al. by way of Huerta et al., so the experiment can be rebuilt line for line. The minimum stall values themselves are missing from the text. Four can be reconstructed by adding the producer stalls in each snippet, but that is inference from the listings, not the author's reported measurement. It was done by a single author on a single architecture, with no second run to confirm it.

AdoptionInsufficient

One session on one architecture

The only observable use is the author's own measurement run. No other party reproduces the numbers, and no compiler, library or kernel is shown behaving differently because of them.

Hype gap+20

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