The person this lands on is a process integration engineer in a Chinese fab with one slot free on the qualification calendar and a choice about which layer to risk. Deposition is not one job. The layers a deposition tool puts down can be conductors, insulators or semiconductor material, and some are only a few nanometers thick [5]. A chamber laying a forgiving film and a chamber that has to hold a few nanometers wafer after wafer are different purchases. A launch announcement counts them as the same unit.
A fab actually does something specific with a new equipment supplier: it runs the tool on a layer that tolerates error, alongside the incumbent tool, until the numbers hold. A six-tool slide invites a different conclusion: that four categories were crossed in an afternoon. AMEC itself says the six machines are at different stages of commercialization and that not all of them have entered large-scale use in factories [7], and moving from a working machine to volume deployment means extensive testing and customer qualification, with equipment expected to hold precision and repeatability while running continuously [8].
The unit arithmetic is worth doing plainly. Four deposition tools out of six is about two thirds of the launch by count [11], which leaves two machines to cover both the etch line AMEC already owns and the silicon-carbide equipment [12]. So the deposition share is not a rounding artifact of a broad catalogue drop. It is the point of the drop, from a company whose business was built around etch [4].
The material leaves the choke-point story unsupported. The report does not say which of the six are running production wafers, does not name a customer, and does not give a target node [13]. Chinese chipmakers are still dependent on overseas suppliers across several equipment categories, and US and allied export restrictions have limited access to some of the most advanced tools [10]. A wider domestic catalogue is consistent with those restrictions biting less over time. It is not evidence that they have.
The number that would settle it is steps run, not products announced. Modern chips can need hundreds of processing steps, cycling through deposition, patterning and etch [6]. Localization is the count of those steps a domestic tool runs on production wafers today, plus the repeat orders that follow a passed qualification.
A forcing function for anyone with this decision, in China or anywhere a single supplier category has been cut off. Draw two axes: how critical the layer is, and how proven the tool is in volume. Proven tool, non-critical layer is where a second source belongs. Proven tool, critical layer is the real win and is rare. Demo tool, non-critical layer is honest pilot work and costs you a quarter. Demo tool, critical layer is where a supply constraint quietly pushes you, because there is no import alternative to compare against, and that is the quadrant to refuse in writing.
The recommendation, with its cost attached: put new deposition chambers on the forgiving layers first and accept that your localization percentage moves slower than your supplier's product count, because a repeatability miss at a critical layer buys you the qualification cycle twice.
